Agilent Technologies E5900B User Manual page 59

Configuring the Emulator
Configuring the Emulation Probe for Maximum Performance (BDM)
When to decrease DSCK speed
Emulation probes are configured at the factory with a default DSCK speed.
This speed is suitable for most applications. However, this speed may be too
high if the processor is being operated below the indicated default
Microprocessor System Clock Speed. For speed settings above the factory
default, trace lengths from the processor to the BDM connector must be short
(less than about 5 centimeters or 2 inches), and without stubs. If the
emulation probe cannot communicate reliably with the target system the
DSCK speed must be reduced.
When to increase DSCK speed
Some target systems will allow DSCK speeds greater than the default. The real
maximum speed for a given target system can be determined empirically by
increasing the speed and observing if the communication to the target is
reliable. However, please note that using a Microprocessor System Clock
Speed setting higher than the actual processor capabilities (for example,
settings above "25" for a 25 MHz processor) is not officially supported by
Agilent or the chip manufacturer.
Manufacturer
BDM
Spec. Max DSCK
Processor
(MHz)
MPC8xx CLKOUT/3
58
Emulation Probe
Factory Default
DSCK (MHz)
1 MHz
E5900B / E5901B User's Guide Supplement
Emulation
Probe Max
DSCK (MHz)
26 MHz