Agilent Technologies E5900B User Manual page 63

Coordinating Logic Analysis with Processor Execution
This chapter describes how to use a logic analyzer and an emulation probe
together to gain insight into your target system.
Before you trigger a logic analyzer (or another module) from the emulation
module, you should understand a few things about the emulation module
trigger:
The Emulation Probe TRIG OUT Signal
The trigger signal coming from the emulation probe is an "In Background
Debug Monitor" ("In Monitor") signal. This may cause confusion because a
variety of conditions could cause this signal and falsely trigger your analyzer.
The "In Monitor" trigger signal can be caused by:
• The most common method to generate the signal is to use the emulation
probe to run then break processor execution (select 5XQ and then select
%UHDN in the Emulation Control Interface). Going from "Run" (Running User
Program) to "Break" ("In Monitor") generates the trigger signal.
• Another method to generate the "In Monitor" signal is to use the emulation
probe to reset then break the processor. Going from the reset state of the
processor to the "In Monitor" state will generate the signal.
• In addition, an "In Monitor" signal is generated any time a debugger or
other user interface reads a register, reads memory, sets breakpoints or
steps. Care must be taken to not falsely trigger the logic analyzers listening
to the "In Monitor" signal.
Debuggers can cause triggers
Emulation module user interfaces may introduce additional states into your
analysis measurement and in some cases falsely trigger your analysis
measurement.
When a debugger causes your target to break into monitor it will typically read
memory around the program stack and around the current program counter.
This will generate additional states which appear in the listing.
You can often distinguish these additional states because the time tags will be
in the microsecond and millisecond range. You can use the time tag
information to determine when the processor went into monitor. Typically the
time between states will be in the nanoseconds while the processor is running
and will be in the microsecond and millisecond range when the debugger has
halted the processor and is reading memory.
Note also that some debugger commands may cause the processor to break
62 E5900B / E5901B User's Guide Supplement