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10.3.3 Clock Supply in DEBUG Mode
The CLK_SVD supply during DEBUG mode should be controlled using the SVDCLK.DBRUN bit.
The CLK_SVD supply to SVD is suspended when the CPU enters DEBUG mode if the SVDCLK.DBRUN bit =
0. After the CPU returns to normal mode, the CLK_SVD supply resumes. Although SVD stops operating when the
CLK_SVD supply is suspended, the registers retain the status before DEBUG mode was entered.
If the SVDCLK.DBRUN bit = 1, the CLK_SVD supply is not suspended and SVD will keep operating in DEBUG
mode.
10.4 Operations
10.4.1 SVD Control
Starting detection
SVD should be initialized and activated with the procedure listed below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Configure the operating clock using the SVDCLK.CLKSRC[1:0] and SVDCLK.CLKDIV[2:0] bits.
3. Set the following SVDCTL register bits:
- SVDCTL.VDSEL bit
- SVDCTL.SVDSC[1:0] bits
- SVDCTL.SVDC[4:0] bits
- SVDCTL.SVDRE[3:0] bits
- SVDCTL.SVDMD[1:0] bits
4. Set the following bits when using the interrupt:
- Write 1 to the SVDINTF.SVDIF bit.
- Set the SVDINTE.SVDIE bit to 1.
5. Set the SVDCTL.MODEN bit to 1.
6. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
Terminating detection
Follow the procedure shown below to stop SVD operation.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Write 0 to the SVDCTL.MODEN bit.
3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
Reading detection results
The following two detection results can be obtained by reading the SVDINTF.SVDDT bit:
• Power supply voltage (V
• Power supply voltage (V
Before reading the SVDINTF.SVDDT bit, wait for at least SVD circuit enable response time after 1 is written
to the SVDCTL.MODEN bit (refer to "Supply Voltage Detector Characteristics, SVD circuit enable response
time t
" in the "Electrical Characteristics" chapter).
SVDEN
After the SVDCTL.SVDC[4:0] bits setting value is altered to change the SVD detection voltage V
SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVDINTF.SVDDT
bit (refer to "Supply Voltage Detector Characteristics, SVD circuit response time t
acteristics" chapter).
S1C17W22/W23 TECHNICAL MANUAL
(Rev. 1.3)
or EXSVD) ≥ SVD detection voltage V
DD
or EXSVD) < SVD detection voltage V
DD
Seiko Epson Corporation
10 SUPPLY VOLTAGE DETECTOR (SVD)
(Select detection voltage (V
(Set low power supply voltage detection counter)
(Set SVD detection voltage V
(Select reset/interrupt mode)
(Set intermittent operation mode)
(Clear interrupt flag)
(Enable SVD interrupt)
(Enable SVD detection)
(Disable SVD detection)
when SVDINTF.SVDDT bit = 0
SVD
when SVDINTF.SVDDT bit = 1
SVD
or EXSVD))
DD
)
SVD
when the
SVD
" in the "Electrical Char-
SVD
10-3
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