Table of Contents
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Code No.
Page
412690402
17-12
REMC: REMC Carrier Modulation Control Register - Bit 0 CARREN
(Old) No description
(New) Note: When carrier modulation is disabled, the REMDBCTL.REMOINV bit should be set to 0.
20-6
ADC12A: ADC12A Ch.n Control Register - Bits 14–12 ADSTAT[2:0]
(Old) These bits indicate the pin number that follows the last converted analog input pin after A/D con-
(New) These bits indicate the last converted analog input pin number after A/D conversion is forcefully
20-7
ADC12A: ADC12A Ch.n Control Register - Bit 10 BSYSTAT
(Old) No description
(New) Note: The ADC12_nCTL.BSYSTAT bit is cleared to 0 when the clock is supplied to ADC12A by set-
ADC12A: ADC12A Ch.n Control Register - Bit 1 ADST
(Old) No description
(New) Note: The data written to the ADC12_nCTL.ADST bit must be retained for one or more CLK_T16_k
20-9
ADC12A: ADC12A Ch.n Configuration Register - Bits 1–0 VRANGE[1:0]
(Old) No description
(New) Notes: ...
23-4
Electrical Characteristics: #RESET pin characteristics
Modified the table (The VT+ Max. value and VT- Min. value were modified.)
23-5
Electrical Characteristics: OSC3 oscillator circuit characteristics
Modified the table (The f
23-6
Electrical Characteristics: OSC3 internal oscillation frequency-temperature characteristic, OSC3 internal
oscillation frequency-power supply voltage characteristic
Corrected the graphs (The CLGOSC3.OSC3FQ[1:0] bit values were corrected.)
Electrical Characteristics: EXOSC external clock input characteristics
Modified the table (The VT+ Max. value, VT- Min. value, and DV
23-7
Electrical Characteristics: Input/Output Port (PPORT) Characteristics
Modified the table (The VT+ Max. value, VT- Min. value, and DV
23-9
Electrical Characteristics: Supply Voltage Detector (SVD) Characteristics
Modified the figure (SVDCTL.SVDSC[1:0] = 0x1f → SVDCTL.SVDC[4:0] = 0x1e)
23-16
Electrical Characteristics: R/F Converter (RFC) Characteristics
Modified the table (The VT+ Max. value, VT- Min. value, and DV
23-17
Electrical Characteristics: 12-bit A/D Converter (ADC12A) Characteristics
Modified the table (The f
24-3
Basic External Connection Diagram: Sample external components
(Old) X'tal3 | Crystal resonator | CA-301 (1 MHz) manufactured by Seiko Epson Corporation
(New) X'tal3 | Crystal resonator | CA-301 (4 MHz) manufactured by Seiko Epson Corporation
AP-A-2
List of Peripheral Circuit Control Registers: CLG OSC3 Control Register
Modified the register table (OSC3WT[2:0]: Initial = 0x6 → 0x0)
AP-A-3
List of Peripheral Circuit Control Registers: ITC Interrupt Level Setup Register 8
Modified the register table ((S1C17W23 only) was deleted.)
AP-A-4
List of Peripheral Circuit Control Registers: WDT Control Register
Modified the register table (NMIXRST, STATNMI → Reserved)
AP-A-16 to
List of Peripheral Circuit Control Registers: T16B Ch.n Compare/Capture m Data Register
AP-A-19
Modified the register table (CC[15:0]: Initial = 0xffff → 0x0000)
AP-A-22
List of Peripheral Circuit Control Registers: 0x5320–0x5332
(Old) IR Remote Controller (REMC) (S1C17W23 only)
(New) IR Remote Controller (REMC)
AP-C-1
Mounting Precautions: V
(Old) Connect C
(New) If fluctuations in the Flash programming voltage V
AP-C-2
Mounting Precautions: Unused pins
(Old) (4) CV1–2 pins
(New) (4) CV1–2 pins
version is forcefully terminated by writing 0 to the ADC12_nCTL.ADST bit or automatically termi-
nated in one-time conversion mode (ADC12_nTRG.CNVMD = 0).
terminated by writing 0 to the ADC12_nCTL.ADST bit or automatically terminated in one-time con-
version mode (ADC12_nTRG.CNVMD = 0).
ting the ADC12_nCTL.MODEN bit to 1.
clock cycles when 1 is written or two or more CLK_T16_k clock cycles when 0 is written.
• Be aware that ADC circuit current I
to 0x3 when the ADC12_nCTL.BSYSTAT bit = 1.
conditions (CLGOSC3.OSC3FQ[1:0] bit values) were corrected.)
OSC3I
CLK_ADC12A
pin
PP
to this pin if the V
VPP
V
and V
pins to suppress fluctuations within V
SS
PP
the V
pin as possible and use a sufficiently thick wiring pattern that allows current of several tens
PP
of mA to flow.
Added a figure (V
pin connection example)
PP
If super economy mode is not used, these pins should be left open.
If super economy mode is not used, the C
can be omitted by connecting between the V
short-circuited, C
is required even if super economy mode is not used.
PW3
Contents
flows if the ADC12_nCFG.VRANGE[1:0] bits are set
ADC
T
T
T
Max. value was modified.)
voltage is not stable.
PP
is large, connect a capacitor C
PP
± 1 V. The C
PP
and C
pins should be left open. In this case, C
V1
V2
and V
DD
D2
REVISION HISTORY
Min. value were modified.)
Min. value were modified.)
Min. value were modified.)
between the
VPP
should be placed as close to
VPP
pins directly. When these pins are not
PW3
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