10-Bit Addressing In Master Mode - Epson S1C17W22 Technical Manual

14.4.4 10-bit Addressing in Master Mode

A 10-bit address consists of the first address that contains two high-order bits and the second address that contains
eight low-order bits.
7-bit address
10-bit address
First address
Second address
The following shows a procedure to start data transfer in 10-bit address mode when the I2C Ch.n is placed into
master mode (see the 7-bit mode descriptions above for control procedures when a NACK is received or sending/
receiving data). Figure 14.4.4.2 shows an operation example.
Starting data transmission in 10-bit address mode
1. Issue a START condition by setting the I2CnCTL.TXSTART bit to 1.
2. Wait for a transmit buffer empty interrupt (I2CnINTF.TBEIF bit = 1) or a START condition interrupt (I2C-
nINTF.STARTIF bit = 1).
Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred.
3. Write the first address to the I2CnTXD.TXD[7:1] bits and 0 that represents WRITE as the data transfer di-
rection to the I2CnTXD.TXD0 bit.
4. Wait for a transmit buffer empty interrupt (I2CnINTF.TBEIF bit = 1).
5. Write the second address to the I2CnTXD.TXD[7:0] bits.
6. Wait for a transmit buffer empty interrupt (I2CnINTF.TBEIF bit = 1).
7. Perform data transmission.
Starting data reception in 10-bit address mode
1 to 6. These steps are the same as the data transmission starting procedure described above.
7. Issue a repeated START condition by setting the I2CnCTL.TXSTART bit to 1.
8. Wait for a transmit buffer empty interrupt (I2CnINTF.TBEIF bit = 1) or a START condition interrupt (I2C-
nINTF.STARTIF bit = 1).
Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred.
9. Write the first address to the I2CnTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direc-
tion to the I2CnTXD.TXD0 bit.
10. Perform data reception.
S1C17W22/W23 TECHNICAL MANUAL
(Rev. 1.3)
D7 D6 D5 D4 D3
A6 A5 A4 A3 A2
Slave address
D7 D6 D5 D4 D3
1 1 1 1 0
Two high-order slave address bits
D7 D6 D5 D4 D3
A7 A6 A5 A4 A3
Eight low-order slave address bits
Figure 14.4.4.1 10-bit Address Configuration
Seiko Epson Corporation
D2 D1 D0
A1 A0 R/W
0: WRITE (Master
1: READ (Slave
D2 D1 D0
A9 A8 R/W
D2 D1 D0
A2 A1 A0
14 I 2 C (I2C)
→
Slave)
→
Master)
14-9