Operations; Initialization; Conversion Start Trigger Source - Epson S1C17W22 Technical Manual

For the R and C
ADIN ADIN
"Electrical Characteristics" chapter. Based on these values, configure the ADC12A operating clock CLK_T16_k
and the ADC12_nTRG.SMPCLK[2:0] bits that set the sampling time so that these settings will satisfy the equations
shown below.
t = 8 × (R + R
ACQ S ADIN
1
— — — — — — × SMPCLK > t
f
CLK_ADC
Where
f : CLK_T16_k frequency [Hz]
CLK_ADC
SMPCLK: Sampling time = ADC12_nTRG.SMPCLK[2:0] bit-setting (4 to 11 CLK_T16_k cycles)
The following shows the relationship between the sampling time and the maximum sampling rate.
Maximum sampling rate [sps] = — — — — — — — — — —

20.4 Operations

20.4.1 Initialization

The ADC12A should be initialized with the procedure shown below.
1. Assign the ADC12A input function to the ports. (Refer to the "I/O Ports" chapter.)
2. Configure the 16-bit timer Ch.k operating clock so that it will satisfy the sampling time.
3. Set the ADC12_nCTL.MODEN bit to 1.
4. Configure the following ADC12_nTRG register bits:
- ADC12_nTRG.SMPCLK[2:0] bits
- ADC12_nTRG.CNVTRG[1:0] bits
- ADC12_nTRG.CNVMD bit
- ADC12_nTRG.STMD bit
- ADC12_nTRG.STAAIN[2:0] bits
- ADC12_nTRG.ENDAIN[2:0] bits
5. Set the ADC12_nCFG.VRANGE[1:0] bits to 0x3. (Set operating voltage range according to V
6. Set the following bits when using the interrupt:
- Write 1 to the interrupt flags in the ADC12_nINTF register.
- Set the interrupt enable bits in the ADC12_nINTE register to 1. (Enable interrupts)

20.4.2 Conversion Start Trigger Source

The trigger source, which starts A/D conversion, can be selected from the three types shown below using the
ADC12_nTRG.CNVTRG[1:0] bits.
External trigger (#ADTRGn pin)
Writing 1 to the ADC12_nCTL.ADST bit enables the ADC12A to accept trigger inputs. After that, the falling
edge of the signal input to the #ADTRGn pin starts A/D conversion.
16-bit timer Ch.k underflow trigger
Writing 1 to the ADC12_nCTL.ADST bit enables the ADC12A to accept trigger inputs. After that, A/D conver-
sion is started when an underflow occurs in the 16-bit timer Ch.k.
Software trigger
Writing 1 to the ADC12_nCTL.ADST bit starts A/D conversion.
Trigger inputs can be accepted while the ADC12_nCTL.BSYSTAT bit is set to 0 and are ignored while set to 1.
A/D conversion is actually started in sync with CLK_T16_k after a trigger is accepted.
Writing 0 to the ADC12_nCTL.ADST bit stops A/D conversion after the one currently being executed has com-
pleted.
S1C17W22/W23 TECHNICAL MANUAL
(Rev. 1.3)
values in the equivalent circuit, refer to "12-bit A/D Converter Characteristics" in the
) × C
ADIN
ACQ
f
CLK_ADC
SMPCLK + 13
Seiko Epson Corporation
20 12-BIT A/D CONVERTER (ADC12A)
(Eq. 20.1)
(Eq. 20.2)
(Eq. 20.3)
(Enable ADC12A operations)
(Set sampling time)
(Select conversion start trigger source)
(Set conversion mode)
(Set data storing mode)
(Set analog input pin to be A/D converted first)
(Set analog input pin to be A/D converted last)
(Clear interrupt flags)
)
DD
20-3