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REVISION HISTORY
Code No.
Page
412690402
6-5
PPORT: Reading input data from a GPIO port
(Old) No description
(New) Note: The PxDAT.PxINy bit retains the input port status at 1 clock before being read from the CPU.
PPORT: Chattering filter function
(Old) Input sampling time [second] = 2 / CLK_PPORT frequency [Hz] (Eq.6.2)
(New) Input sampling time [second] = 2 to 3 / CLK_PPORT frequency [Hz] (Eq.6.2)
6-8
PPORT: Px Port Interrupt Control Register
(Old) Note: To prevent generating unnecessary interrupts, clear the corresponding interrupt flag before
(New) Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be
8-1
WDT: Overview
(Old) • Includes a 10-bit up counter to count NMI/reset generation cycle.
(New) • Includes a 10-bit up counter to count reset generation cycle.
WDT: Figure 8.1.1 WDT Configuration
Modified the figure (NMIXRST, STATNMI, and the NMI output were deleted.)
WDT: WDT Operating Clock
(Old) Use the following equation to calculate the WDT counter overflow cycle (NMI/reset generation
(New) Use the following equation to calculate the WDT counter overflow cycle (reset generation cycle).
8-2
WDT: Starting up WDT
(Old) 3. Configure the WDTCTL.NMIXRST bit. (Select NMI or reset mode)
(New) 3. Write 1 to the WDTCTL.WDTCNTRST bit. (Reset WDT counter)
WDT: Resetting WDT
(Old) WDT generates a system reset (WDTCTL.NMIXRST bit = 0) or NMI (WDTCTL.NMIXRST bit = 1)
(New) WDT generates a system reset when the counter overflows. ...
WDT: During HALT mode
(Old) WDT operates in HALT mode. HALT mode is therefore cleared by an NMI or reset if it continues for
(New) WDT operates in HALT mode. HALT mode is therefore cleared by a reset if it continues for more
WDT: During SLEEP mode
(Old) WDT operates in SLEEP mode if the selected clock source is running. In this case SLEEP mode is
(New) WDT operates in SLEEP mode if the selected clock source is running. In this case SLEEP mode is
8-3
WDT: WDT Control Register
Modified the register table (NMIXRST, STATNMI → Reserved)
WDT: WDT Control Register
(Old) Bits 15–10 Reserved
(New) Bits 15–5 Reserved
enabling interrupts.
cleared before enabling interrupts.
...
• Counter overflow generates a reset or NMI.
...
• Counter overflow generates a reset.
cycle).
4. Write 1 to the WDTCTL.WDTCNTRST bit. (Reset WDT counter)
5. Write a value other than 0xa to the WDTCTL.WDTRUN[3:0] bits. (Start up WDT)
6. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
4. Write a value other than 0xa to the WDTCTL.WDTRUN[3:0] bits. (Start up WDT)
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
when the counter overflows. ...
After resetting, WDT starts counting with a new NMI/reset generation cycle. If WDT is not reset
within the t
cycle for any reason, the CPU is switched to interrupt processing by NMI or reset,
WDT
the interrupt vector is read out, and the interrupt handler routine is executed. If the counter over-
flows and generates an NMI without WDT being reset, the WDTCTL.STATNMI bit is set to 1.
After resetting, WDT starts counting with a new reset generation cycle. If WDT is not reset within
the t
cycle for any reason, a system reset is generated.
WDT
more than the NMI/reset generation cycle and the NMI or reset handler is executed.
than the reset generation cycle and the reset handler is executed.
cleared by an NMI or reset if it continues for more than the NMI/reset generation cycle and the NMI
or reset handler is executed. ...
If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary
NMI or reset after clearing SLEEP mode, reset WDT before executing the slp instruction.
cleared by a reset if it continues for more than the reset generation cycle and the reset handler is
executed. ...
If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary
reset after clearing SLEEP mode, reset WDT before executing the slp instruction.
Bit 9 N MIXRST
...
Bit 8 STATNMI
...
Bits 7–5 Reserved
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