Epson S1C17W22 Technical Manual page 39

2 POWER SUPPLY, RESET, AND CLOCKS
System clock switching
The CPU boots using IOSCCLK as SYSCLK. After booting, the clock source of SYSCLK can be switched ac-
cording to the processing speed required. The SYSCLK frequency can also be set by selecting the clock source
division ratio, this makes it possible to run the CPU at the most suitable performance for the process to be ex-
ecuted. The CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are used for this control.
The CLGSCLK register bits are protected against writings by the system protect function, therefore, the system
protection must be removed by writing 0x0096 to the MSCPROT.PROT[15:0] bits before the register setting can
be altered. For the transition between the operating modes including the system clock switching, refer to "Oper-
ating Mode."
Clock control in SLEEP mode
The CPU enters SLEEP mode when it executes the slp instruction. Whether the clock sources being operated
are stopped or not at this point can be selected in each source individually. This allows the CPU to fast switch
between SLEEP mode and RUN mode, and the peripheral circuits to continue operating without disabling
the clock in SLEEP mode. The CLGOSC.IOSCSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3SLPC, and
CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.3 shows a control example.
(1) When the CLGOSC.OSC1SLPC bit = 1
SYSCLK
(CPU operating clock)
LCD driver
operating clock
(2) When the CLGOSC.OSC1SLPC bit = 0
SYSCLK
(CPU operating clock)
LCD driver
operating clock
The SYSCLK condition (clock source and division ratio) at wake-up from SLEEP mode to RUN mode can also
be configured. This allows flexible clock control according to the wake-up process. Configure the clock using
the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit
to enable this function.
(1) When the CLGSCLK.WUPMD bit = 0
SYSCLK
(CPU operating clock)
(2) When the CLGSCLK.WUPMD bit = 1 and the CLGSCLK.WUPSRC[1:0] bits = 0x0
SYSCLK
(CPU operating clock)
2-12
IOSCCLK
(CPU stop, CLK stop)
Executing the
slp instruction
OSC1CLK
∗ The LCD display is turned off in
SLEEP mode as the clock stops.
IOSCCLK
(CPU stop, CLK stop)
Executing the
slp instruction
∗ The LCD display continues in
SLEEP mode as the clock is being supplied.
Figure 2.3.4.3 Clock Control Example in SLEEP Mode
OSC1CLK
Executing the
slp instruction
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x1 (OSC1)
OSC1CLK
Executing the
slp instruction
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
Figure 2.3.4.4 Clock Control Example at SLEEP Cancelation
Seiko Epson Corporation
Oscillation stabilization waiting time
SLEEP mode
IOSCCLK
(Unstable)
Interrupt
(Wake-up)
OSC1CLK
(CLK stop)
(Unstable)
SLEEP mode IOSCCLK
(Unstable)
Interrupt
(Wake-up)
OSC1CLK
SLEEP mode
(CPU stop, CLK stop)
Interrupt
(Wake-up)
∗ Starting up with the same clock as one
that used before SLEEP mode was entered.
SLEEP mode IOSCCLK
(CPU stop, CLK stop)
(Unstable)
Interrupt
(Wake-up)
CLGSCLK.CLKSRC[1:0] = 0x0 (IOSC)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
∗ Switching to IOSC that features fast
initiation allows high-speed processing.
S1C17W22/W23 TECHNICAL MANUAL
IOSCCLK
OSC1CLK
IOSCCLK
Oscillation stabilization waiting time
OSC1CLK
OSC1CLK
(Unstable)
IOSCCLK
(Rev. 1.3)