Table of Contents
Advertisement
18.4.6 LCD Contrast Adjustment
The LCD panel contrast can be adjusted within 32 levels using the LCD24PWR.LC[4:0] bits. This function is real-
ized by controlling the voltage output from the LCD voltage regulator. Therefore, the LCD24PWR.LC[4:0] bits
cannot be used for contrast adjustment in external voltage application modes 1 and 2.
18.5 Operations
18.5.1 Initialization
The LCD24A should be initialized with the procedure shown below.
1. Assign the LCD24A output function to the ports. (Refer to the "I/O Ports" chapter.)
2. Configure the LCD24CLK.CLKSRC[1:0] and LCD24CLK.CLKDIV[2:0] bits. (Configure operating clock)
3. Write 1 to the LCD24CTL.MODEN bit.
4. Configure the following LCD24TIM1 register bits:
- LCD24TIM1.LDUTY[4:0] bits
- LCD24TIM1.COMPOS bit
- LCD24TIM1.FRMCNT[4:0] bits
5. Configure the following LCD24TIM2 register bits:
- LCD24TIM2.NLINE[4:0] bits
- LCD24TIM2.BSTC[1:0] bits
6. Configure the following LCD24PWR register bits:
- LCD24PWR.VCEN bit
- LCD24PWR.VCSEL bit
- LCD24PWR.BISEL bit
- LCD24PWR.BSTEN bit
- LCD24PWR.LC[4:0] bits
7. Configure the following LCD24DSP register bits:
- LCD24DSP.DSPAR bit
- LCD24DSP.COMREV bit
- LCD24DSP.SEGREV bit
8. Write display data to the display data RAM.
9. Set the following bits when using the interrupt:
- Write 1 to the LCD24INTF.FRMIF bit.
- Set the LCD24INTE.FRMIE bit to 1.
18.5.2 Display On/Off
The LCD display state is controlled using the LCD24DSP.DSPC[1:0] bits.
When "Display off" is selected, the drive voltage supply stops and the LCD driver pin outputs are all set to V
level.
Since "All on" and "All off" directly control the driving waveform output by the LCD driver, data in the display
data RAM is not altered. The common pins are set to dynamic drive for "All on" and to static drive for "All off."
This function can be used to make the display flash on and off without altering the display memory.
S1C17W22/W23 TECHNICAL MANUAL
(Rev. 1.3)
Table 18.5.2.1 LCD Display Control
LCD24DSP.DSPC[1:0] bits
0x3
0x2
0x1
0x0
Seiko Epson Corporation
(Enable LCD24A operating clock)
(Set drive duty)
(Set COM[7:0] pin layout)
(Set frame frequency)
(Set n-line inverse AC drive)
(Set booster clock frequency)
(Enable LCD voltage regulator)
(Set reference voltage for boosting)
(Set bias)
(Enable LCD voltage booster)
(Set LCD contrast initial value)
(Select display area)
(Select COM pin assignment direction)
(Select SEG pin assignment direction)
(Clear interrupt flag)
(Enable LCD24A interrupt)
LCD display
All off (static drive)
All on
Normal display
Display off
18 LCD DRIVER (LCD24A)
SS
18-7
Advertisement
Table of Contents
