Switches - Xilinx ZC702 User Manual

Figure 1-25 shows the user GPIO male pin header circuits.
X-Ref Target - Figure 1-25
J62
Table 1-27 lists the GPIO Header connections to XC7Z020 AP SoC U1.
Table 1-27: GPIO Header Connections to XC7Z020 AP SoC at U1
XC7Z020 AP SoC (U1) Pin
E15
D15
W17
W5
V7
W10
P18
P17
Refer to the Zynq-7000 All Programmable SoC Technical Reference Manual (UG585)
for information about the PS PJTAG functionality.

Switches

[Figure 1-2, callout 22–26]
The ZC702 board includes a power and a configuration switch:
• Power On/Off slide switch SW11 (callout 26)
• SW4 (FPGA_PROG_B), active-Low pushbutton (callout 22)
ZC702 Board User Guide
UG850 (v1.3) June 4, 2014
VCC3V3
PMOD2 0
1
2 PMOD2 1
PMOD2 2
3
PMOD2 3
4
5
6
GND
Figure 1-25: User GPIO Headers
Net Name
PMOD1_0
PMOD1_1
PMOD1_2
PMOD1_3
PMOD2_0
PMOD2_1
PMOD2_2
PMOD2_3
www.xilinx.com
VCC3V3 VCC3V3
J63
PMOD1 0 1 2
PMOD1 1 3 4
PMOD1 2 5 6
PMOD1 3 7 8
9 10
11 12
GND GND
GPIO Header and Pin
J63.1
J63.3
J63.5
J63.7
J62.1
J62.2
J62.3
J62.4
Feature Descriptions
PL PJTAG TDI LS
PL PJTAG TMS LS
PL PJTAG TCK LS
PL PJTAG TDO LS
UG850_c1_25_030513
[Ref 9]
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