Xilinx ZC702 User Manual page 22

Table 1-6 describes the jumper settings for the USB 2.0 circuit. Bold text identifies the
default shunt positions for USB 2.0 high speed on-the-go (OTG) mode.
Table 1-6: USB Jumper Settings
Header Function
J44 USB PHY reset
J7 VBUS 5V
supply
J33 RVBUS select
J35 CVBUS select
J34 Cable ID select
J36 USB Micro-B
The connections between the USB Mini-B connector at J1 and the PHY at U9 are listed in
Table 1-7.
Table 1-7: USB Connector Pin Assignments and Signal Definitions Between J1 and U9
USB Connector
J1
Pin Name
1 VBUS USB_VBUS_SEL
2 D_N USB_D_N
3 D_P USB_D_P
5 GND GND
The connections between the USB 2.0 PHY at U9 and the XC7Z020 AP SoC are listed in
Table 1-8.
Table 1-8: USB 2.0 ULPI Transceiver Connections to the XC7Z020 AP SoC
XC7Z020 (U1)
Pin Name Bank
PS_MIO36 501
PS_MIO31 501
PS_MIO32 501
PS_MIO33 501
PS_MIO34 501
ZC702 Board User Guide
UG850 (v1.3) June 4, 2014
Shunt Position
Shunt ON = USB PHY reset
Shunt OFF = USB PHY normal operation
Shunt ON = Host or OTG mode
Shunt OFF = Device mode
Position 1–2 = Device mode (10 kΩ)
Position 2–3 = OTG mode (1 kΩ)
Position 1-2 = OTG and Device mode (1 μ F)
Position 2-3 = Host mode (120 μ F)
Position 1-2 = A/B cable detect
Position 2-3 = ID not used
Position 1-2 = Shield connected to GND
Position 2-3 = Shield floating
Net Name
+5V from host system
Bidirectional differential serial data (N-side)
Bidirectional differential serial data (P-side)
Signal ground
Pin Number
A9
F9
C7
G13
B12
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Clean reset requires external
debouncing
Overvoltage protection
VBUS load capacitance
Used in OTG mode.
Description
Schematic Net Name
USB_CLKOUT
USB_NXT
USB_DATA0
USB_DATA1
USB_DATA2
Feature Descriptions
Notes
USB3320 (U9)
Pin
22
19
18
33
USB3320 (U9) Pin
1
2
3
4
5
22
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