Xilinx ZC702 User Manual page 13

The high-level block diagram is shown in
X-Ref Target - Figure 1-3
Processing
Input Output
Peripherals
High-Bandwidth
®
AMBA
The PS integrates two ARM® Cortex™-A9 MPCore™ application processors, AMBA®
interconnect, internal memories, external memory interfaces, and peripherals including
USB, Ethernet, SPI, SD/SDIO, I
and boots at power-up or reset.
ZC702 Board User Guide
UG850 (v1.3) June 4, 2014
System
(PS)
(IOP)
AXI Interfaces
Common Accelerators
Figure 1-3: High-Level Block Diagram
2
C, CAN, UART, and GPIO. The PS runs independently of the PL
www.xilinx.com
Figure 1-3.
Memory
Interfaces
Application
Processor Unit (APU)
Interconnect
Custom Accelerators
Feature Descriptions
Programmable
Logic
(PL)
Common
Peripherals
Custom
Peripherals
UG850_c1_03_081612
13
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