Xilinx ZC702 User Manual page 52

The LPC connections between FMC1 (J3) and XC7Z020 AP SoC U1
FMC2 (J4) and XC7Z020 AP SoC U1
connectivity:
• 68 single-ended or 34 differential user-defined signals (34 LA pairs, LA00–LA33)
• 0 GTX transceivers
• 0 GTX clocks
• 2 differential clocks
• 61 ground and 9 power connections
FMC1 (J3) and FMC2 (J4) GA0 = GA1 = 0 (GND).
Note:
Table 1-28 shows the LPC connections between J3 and XC7Z020 AP SoC U1.
Table 1-28: LPC Connections, FMC1 (J3) to XC7Z020 AP SoC U1
FMC1
Net Name
J3 Pin
C2 NC
C3 NC
C6 NC
C7 NC
C10 FMC1_LPC_LA06_P
C11 FMC1_LPC_LA06_N
C14 FMC1_LPC_LA10_P
C15 FMC1_LPC_LA10_N
C18 FMC1_LPC_LA14_P
C19 FMC1_LPC_LA14_N
C22 FMC1_LPC_LA18_CC_P
C23 FMC1_LPC_LA18_CC_N
C26 FMC1_LPC_LA27_P
C27 FMC1_LPC_LA27_N
C30 FMC1_LPC_IIC_SCL
C31 FMC1_LPC_IIC_SDA
C34 GA0 = 0 = GND
C35 VCC12_P
C37 VCC12_P
C39 VCC3V3
ZC702 Board User Guide
UG850 (v1.3) June 4, 2014
(Table 1-29) both implement a subset of this
XC7Z020 (U1)
J3 Pin
Pin
D1 PWRCTL1_VCC4A_PG
D4 NC
D5 NC
D8 FMC1_LPC_LA01_CC_P
J18 D9 FMC1_LPC_LA01_CC_N
K18 D11 FMC1_LPC_LA05_P
L17 D12 FMC1_LPC_LA05_N
M17 D14 FMC1_LPC_LA09_P
J16 D15 FMC1_LPC_LA09_N
J17 D17 FMC1_LPC_LA13_P
D20 D18 FMC1_LPC_LA13_N
C20 D20 FMC1_LPC_LA17_CC_P
C17 D21 FMC1_LPC_LA17_CC_N
C18 D23 FMC1_LPC_LA23_P
D24 FMC1_LPC_LA23_N
D26 FMC1_LPC_LA26_P
D27 FMC1_LPC_LA26_N
D29 FMC1_LPC_TCK_BUF
D30 FMC_TDI_BUF
D31 FMC1_LPC_TDO_FMC2_LPC_TDI
D32 VCC3V3
D33 FMC1_LPC_TMS_BUF
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Feature Descriptions
(Table 1-28) and between
XC7Z020 (U1)
Net Name
N19
N20
N17
N18
M15
M16
P16
R16
B19
B20
G15
G16
F18
E18
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