Programmable Logic Jtag Programming Options - Xilinx ZC702 User Manual

Table 1-9 lists the SD card interface connections to the XC7Z020 AP SoC.
Table 1-9: SDIO Connections to the XC7Z020 AP SoC
XC7Z020 (U1) Pin
Pin Name Bank
PS_MIO15 500
PS_MIO0 500
PS_MIO41 501
PS_MIO40 501
PS_MIO42 501
PS_MIO45 501
PS_MIO44 501
PS_MIO43 501

Programmable Logic JTAG Programming Options

[Figure 1-2, callout 6]
The ZC702 board JTAG chain is shown in
X-Ref Target - Figure 1-9
J2
JTAG
Header
TDO
TDI
U75
U76
U23
U77
JTAG 3:1
Module Analog
Switch
TDO
TDI
J58
JTAG
Header
TDO
TDI
ZC702 Board User Guide
UG850 (v1.3) June 4, 2014
Schematic
Pin
Net Name
Number
E6 SDIO_SDWP
G6 SDIO_SDDET
C8 SDIO_CMD_LS
E14 SDIO_CLK_LS
D8 SDIO_DAT2_LS
B9 SDIO_DAT1_LS
E13 SDIO_DAT0_LS
B11 SDIO_CD_DAT3_LS
Figure
SPST Bus Switch
U25
N.C.
J3
FMC LPC
Connector
TDI TDO
Figure 1-9: JTAG Chain Block Diagram
www.xilinx.com
Level Shifter (U61)
(A) Pin (B) Pin
Number Number
N/A N/A
N/A N/A
4 20
9 19
1 23
7 16
6 18
3 22
1-9.
SPST Bus Switch
U26
N.C.
3.3V 2.5V
J4
U39
FMC LPC
Connector
SN74AVC1T45
Voltage
Translator
TDI TDO TDI
U38
SN74AVC1T45
Voltage
Translator
TDO
Feature Descriptions
SDIO Connector (J64)
Pin Pin
Number Name
11 PROTECT
10 DETECT
2 CMD
5 CLK
9 DAT2
8 DAT1
7 DAT0
1 CD_DAT3
U1
Zynq-7000
XC7Z020
AP SoC
TDI
TDO
TDO
TDI
UG850_c1_09_030513
25
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