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Renesas RA0E1 User Manual

32-bit mcu

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RA0E1 Group

32

32-Bit MCU

Renesas Advanced (RA) Family

Renesas RA0 Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.1.10 Dec 2024

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Summary of Contents for Renesas RA0E1

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2: Corporate Headquarters
Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.
Page 3: General Precautions In The Handling Of Microprocessing Unit And Microcontroller Unit Products
Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 4: About This Document
Audience This manual is written for system designers who are designing and programming applications using the Renesas Microcontroller. The user is expected to have basic knowledge of electrical circuits, logic circuits, and the MCU.
Page 5: Typographic Notation
Numbering Notation The following numbering notation is used throughout this manual: Example Description 011b Binary number. For example, the binary equivalent of the number 3 is 011b. 0x1F Hexadecimal number. For example, the hexadecimal equivalent of the number 31 is described 0x1F. In some cases, a hexadecimal number is shown with the suffix "h".
Page 6: Register Description
Register Description Each register description includes both a register diagram that shows the bit assignments and a register bit table that describes the content of each bit. The example of symbols used in these tables are described in the sections that follow. The following is an example of a register description and associated bit field definition.
Page 7 Abbreviations Abbreviations used in this document are shown in the following table. Abbreviation Description Advanced High-performance Bus AHB-AP AHB Access Port Advanced Peripheral Bus APB-AP APB Access Port Binary Coded Decimal Human Machine Interface IrDA Infrared Data Association Least Significant Bit Most Significant Bit Micro Trace Buffer NVIC...
Page 8: Proprietary Notice
All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no...
Page 9: Table Of Contents
Contents Features ................................25 Overview..............................26 Function Outline ..........................26 Block Diagram ............................ 30 Part Numbering ..........................30 Function Comparison ......................... 33 Pin Functions............................34 Pin Assignments..........................36 Pin Lists .............................. 39 CPU ................................40 Overview............................. 40 2.1.1 CPU............................40 2.1.2 Debug............................
Page 10 Register Descriptions ......................... 57 5.2.1 RESF : Reset Status Flag Register..................57 5.2.2 PORSR : Power-On Reset Status Register ................58 Operation............................58 5.3.1 RES Pin Reset ........................58 5.3.2 Power-On Reset........................58 5.3.3 Voltage Monitor Reset......................59 5.3.4 Independent Watchdog Timer Reset..................60 5.3.5 Software Reset........................
Page 11 8.2.10 HOCOCR : High-speed On-chip Oscillator Control Register ..........84 8.2.11 MOCOCR : Middle-speed On-chip Oscillator Control Register..........84 8.2.12 OSTC : Oscillation Stabilization Time Counter Status Register ..........85 8.2.13 OSTS : Oscillation Stabilization Time Select Register ............87 8.2.14 OSCSF : Oscillation Stabilization Flag Register ..............
Page 12 9.5.2 Operating Range......................... 110 Sleep Mode ............................112 9.6.1 Transitioning to Sleep Mode....................112 9.6.2 Canceling Sleep Mode ......................112 Software Standby Mode ........................113 9.7.1 Transition to Software Standby Mode ................. 113 9.7.2 Canceling Software Standby Mode..................113 9.7.3 Example of Software Standby Mode Application ..............
Page 13 11.3 Vector Table............................135 11.3.1 Interrupt Vector Table ......................136 11.3.2 Event Number ........................138 11.4 Interrupt Operation ........................... 139 11.4.1 Detecting Interrupts......................139 11.5 Interrupt setting procedure ....................... 140 11.5.1 Enabling Interrupt Requests....................140 11.5.2 Disabling Interrupt Requests....................140 11.5.3 Polling for Interrupts ......................
Page 14 14.2.2 MRB : DTC Mode Register B ....................152 14.2.3 SAR : DTC Transfer Source Register ................. 153 14.2.4 DAR : DTC Transfer Destination Register................154 14.2.5 CRA : DTC Transfer Count Register A................154 14.2.6 CRB : DTC Transfer Count Register B................155 14.2.7 DTCCR : DTC Control Register ..................
Page 15 15.4.5 Module-Stop Function Setting..................... 179 15.4.6 ELC Delay Time ........................179 15.4.7 Link Availability in Sleep, Software Standby, and Snooze Mode ........180 16. I/O Ports..............................181 16.1 Overview............................181 16.2 Register Descriptions ........................182 16.2.1 PODRm : Pmn Output Data Register (m = 0 to 9, n = 00 to 15) ......... 182 16.2.2 PDRm : Pmn Direction Register (m = 0 to 9, n = 00 to 15) ..........
Page 16 17.2.13 TO0 : Timer Output Register 0 .................... 225 17.2.14 TOL0 : Timer Output Level Register 0 ................226 17.2.15 TOM0 :Timer Output Mode Register 0 ................226 17.2.16 ISC : Input Switch Control Register..................227 17.2.17 TNFEN : TAU Noise Filter Enable Register................. 228 17.2.18 Registers Controlling Port Functions of Pins to be Used for Timer I/O .......
Page 17 18.2.8 ITLS0 : Interval Timer Status Register ................292 18.2.9 ITLMKF0 : Interval Timer Match Detection Mask Register..........294 18.3 Operation............................294 18.3.1 Counter Mode Settings ....................... 294 18.3.2 Capture Mode Settings ....................... 296 18.3.3 Timer Operation ........................297 18.3.4 Capture Operation.......................
Page 18 20.4.1 Refresh Operations ......................331 20.4.2 Clock Division Ratio Setting ....................332 21. Serial Array Unit (SAU) ........................... 333 21.1 Overview............................333 21.1.1 Simplified SPI........................333 21.1.2 UART........................... 334 21.1.3 Simplified I C ........................335 21.2 Configuration of Serial Array Unit ..................... 335 21.3 Register Descriptions ........................
Page 19 21.5.9 Procedure for Processing Errors that Occurred During Simplified SPI Communication ..415 21.6 Operation of UART Communication ....................415 21.6.1 UART Transmission ......................416 21.6.2 UART Reception ......................... 423 21.6.3 Snooze Mode Function ....................... 429 21.6.4 Calculating Baud Rate ......................435 21.6.5 Procedure for Processing Errors that Occurred During UART Communication....
Page 20 22.3.16 Communication Reservation ....................486 22.3.17 Usage Notes ........................488 22.3.18 Communication Operations....................489 22.3.19 Timing of I C Interrupt Request Signal (IICA0_TXRXI) Occurrence ........496 22.4 Timing Charts ........................... 511 23. Serial Interface UARTA (UARTA)......................526 23.1 Overview............................526 23.2 Register Descriptions ........................
Page 21 25.2.8 ADLL : Conversion Result Comparison Lower Limit Setting Register ........ 575 25.2.9 ADTES : A/D Test Register ....................575 25.3 A/D Converter Operations ........................ 576 25.4 Input Voltage and Conversion Results ..................... 577 25.5 A/D Converter Operation Modes ...................... 578 25.5.1 Software Trigger No-wait Mode (Select Mode, Sequential Conversion Mode) ....
Page 22 27.3.2 SRAM Error Sources......................617 27.3.3 Access Cycle........................617 27.3.4 Low-Power Function ......................618 27.4 Usage Notes............................. 618 27.4.1 Instruction Fetch from the SRAM Area ................618 27.4.2 SRAM Store Buffer......................618 28. Flash Memory ............................619 28.1 Overview............................619 28.2 Memory Structure ..........................
Page 23 28.9 Self-programming ..........................643 28.9.1 Overview ..........................643 28.9.2 Background Operation ......................644 28.10 Programming and Erasure ....................... 644 28.10.1 Sequencer Modes ....................... 644 28.10.2 Software Commands......................645 28.10.3 Software Command Usage ....................646 28.11 Reading the Flash Memory ......................657 28.11.1 Reading the Code Flash Memory ..................
Page 24 31.5 Peripheral Function Characteristics....................684 31.5.1 Serial Array Unit (SAU) ....................... 684 31.5.2 UART Interface (UARTA) ....................706 31.5.3 C Bus Interface (IICA) ...................... 707 31.6 Analog Characteristics........................708 31.6.1 A/D Converter Characteristics..................... 708 31.6.2 Temperature Sensor/Internal Reference Voltage Characteristics ........713 31.6.3 POR Characteristics......................
Page 25: Features
User’s Manual ® ® Ultra low power 32 MHz Arm Cortex -M23 core, up to 64-KB code flash memory, 12-KB SRAM, 12-bit A/D Converter, Serial interfaces and Safety features. Features ■ Arm Cortex-M23 Core ■ Operating Temperature and Packages ● Armv8-M architecture ●...
Page 26: Overview
® The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability. ® The MCU in this series incorporates an energy-efficient Arm Cortex -M23 32-bit core, that is particularly well suited for cost-sensitive and low-power applications, with the following features: ●...
Page 27 RA0E1 User's Manual 1. Overview Table 1.3 System (2 of 2) Feature Functional description Clocks ● Main clock oscillator (MOSC) ● Sub-clock oscillator (SOSC) ● High-speed on-chip oscillator (HOCO) ● Middle-speed on-chip oscillator (MOCO) ● Low-speed on-chip oscillator (LOCO) ● Clock output / Buzzer output support section 8, Clock Generation Circuit.
Page 28 RA0E1 User's Manual 1. Overview Table 1.6 Timers (2 of 2) Feature Functional description Realtime Clock (RTC) The Realtime Clock (RTC) has the following features. ● Capable of counting years, months, days of the week, dates, hours, minutes, and seconds, for up to 99 years ●...
Page 29 RA0E1 User's Manual 1. Overview Table 1.11 I/O ports Feature Functional description I/O ports ● I/O ports for the 32-pin LQFP/HWQFN – I/O pins: 26 – Input pins: 3 – Pull-up resistors: 16 – N-ch open-drain outputs: 15 – 5-V tolerance: 2 ●...
Page 30: Block Diagram
RA0E1 User's Manual 1. Overview Block Diagram Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the features. SWCLK Cortex-M23 Core SWDIO Data transfer controller NVIC (DTC) SysTick Bus matrix...
Page 31 Group name Series name RA Family Flash memory Renesas microcontroller Note: Check the order screen for each product on the Renesas website for valid symbols after the #. Figure 1.2 Part numbering scheme Table 1.12 Product list (1 of 2) Operating...
Page 32 RA0E1 User's Manual 1. Overview Table 1.12 Product list (2 of 2) Operating Product part number Package code Code flash Data flash SRAM temperature R7FA0E1053CFJ PLQP0032GB-A 32 KB 1 KB 12 KB -40 to +105°C R7FA0E1053CNH PWQN0032KE-A R7FA0E1053CNK PWQN0024KG-A R7FA0E1053CSC...
Page 33: Function Comparison
RA0E1 User's Manual 1. Overview Function Comparison Table 1.13 Function comparison Parts number Pin count Package LQFP/HWQFN HWQFN LSSOP HWQFN Code flash memory 64 KB 32 KB 64 KB 32 KB 64 KB 32 KB 64 KB 32 KB Data flash memory...
Page 34: Pin Functions
RA0E1 User's Manual 1. Overview Pin Functions Table 1.14 Pin functions (1 of 2) Function Signal Description Power supply Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-µF capacitor. Place the capacitor close to the pin.
Page 35 RA0E1 User's Manual 1. Overview Table 1.14 Pin functions (2 of 2) Function Signal Description I/O ports P008 to P015 General-purpose input/output pins P100 to P103, General-purpose input/output pins P108 to P110, P112 P200 Input General-purpose input pin P201, P206 to P208,...
Page 36: Pin Assignments
RA0E1 User's Manual 1. Overview Pin Assignments Figure 1.3 Figure 1.6 show the pin assignments from the top view. P300/SWCLK P015 P200 P014 P013 P201 RES/P206 P012 P009 P207 P208 P008 P011/VREFL0 P913 P010/VREFH0 P914 Figure 1.3 Pin assignment for LQFP / HWQFN 32-pin (top view) Note: For the QFN package product, solder the exposed die pad to the PCB.
Page 37 RA0E1 User's Manual 1. Overview P108/SWDIO P015 P014 P300/SWCLK P013 exposed P200 P012 die pad P201 P011/VREFL0 RES/P206 P010/VREFH0 P913 Note: For the QFN package product, solder the exposed die pad to the PCB. The potential of the exposed die pad is recommended to design as electrically open.
Page 38 RA0E1 User's Manual 1. Overview P012 P300/SWCLK P011/VREFL0 P200 exposed die pad P010/VREFH0 P201 RES/P206 Note: For the QFN package product, solder the exposed die pad to the PCB. The potential of the exposed die pad is recommended to design as electrically open.
Page 39: Pin Lists
RA0E1 User's Manual 1. Overview Pin Lists Table 1.15 Pin list Pin number Timers Communication interfaces Analogs Power, System, Clock, Debug Interrupt IICA UARTA — — — — — — — — — — — XCIN P215 — — —...
Page 40: Cpu
RA0E1 User's Manual 2. CPU ® ® The MCU is based on the Arm Cortex -M23 core. Overview 2.1.1 ● Arm Cortex-M23 – Revision: r1p0-00rel0 – Armv8-M architecture profile – Main Extension is not implemented – Single-cycle integer multiplier – 19-cycle integer divider ●...
Page 41: Bus Matrix
RA0E1 User's Manual 2. CPU OCD Emulator Access Trace/debug data From: OCD Emulator (SWD) From: System bus Cortex ® -M23 integration Cortex-M23 SWJ-DP CM23 core DAP IC NVIC SRAM APB-AP DBGREG OCDREG To: System control ROM Table AHB-AP Bus matrix To: System bus Figure 2.1...
Page 42: Swd Interface
RA0E1 User's Manual 2. CPU Table 2.1 Implementation options (2 of 2) Option Implementation SYST_CALIB register (0x4000_0147) Bit [31] = 0 Reference clock provided Bit [30] = 1 TENMS value is inexact Bits [29:24] = 0x00 Reserved Bits [23:0] = 0x000147 TENMS: (32768 ×...
Page 43: Trace Control (For The Mtb)
RA0E1 User's Manual 2. CPU 2.4.2.2 Reset In OCD mode, some resets depend on the CPU status and the DBGSTOPCR register setting. Table 2.4 Reset or interrupt and mode setting Control in On-Chip Debug (OCD) mode Reset or interrupt name...
Page 44: Programmers Model
RA0E1 User's Manual 2. CPU Note: MTB_BASE = 0x4001_9000 ® ™ For more information on these registers, see the ARM CoreSight MTB-M23 Technical Reference Manual (ARM DDI 0564C). Note: Do not attempt to access reserved or unused address locations. Programmers Model 2.5.1...
Page 45: Coresight Rom Table
RA0E1 User's Manual 2. CPU Table 2.8 External debug address map Component name Start address End address Note MTB (SRAM area) 0x2000_4000 0x2000_6FFF MTB uses up to 1 KB as trace buffer See reference 6. in section 2.8. References. MTB (SFR area)
Page 46 RA0E1 User's Manual 2. CPU Table 2.11 Non-CoreSight DBGREG registers Name DAP port Address Access size Debug Status Register DBGSTR Port 0 0x4001_B000 32 bits Debug Stop Control Register DBGSTOPCR Port 0 0x4001_B010 32 bits 2.5.5.1 DBGSTR : Debug Status Register...
Page 47: Ocdreg Module
RA0E1 User's Manual 2. CPU Symbol Function — This bit is read as 1. The write value should be 1. 13:2 — These bits are read as 0. The write value should be 0. DBGSTOP_TIM Mask Bit for RTC, TAU, TML32 Reset/Interrupt in the OCD brake mode. In the OCD break mode, the reset/interrupt is masked and each operation is stopped.
Page 48 RA0E1 User's Manual 2. CPU Table 2.13 OCDREG registers Name DAP port Address Access size ID Authentication Code Register 0 IAUTH0 Port 1 0x8000_0000 32 bits ID Authentication Code Register 1 IAUTH1 Port 1 0x8000_0100 32 bits ID Authentication Code Register 2...
Page 49 RA0E1 User's Manual 2. CPU Note 1. Depends on the MCU status. 2.5.6.3 MCUCTRL : MCU Control Register Base address: CPU_OCD = 0x8000_0000 Offset address: 0x0410 Bit position: Bit field: — — — — — — — — — —...
Page 50: Systick Timer
RA0E1 User's Manual 2. CPU SysTick Timer The SysTick timer provides a simple 24-bit down counter. The reference clock for the timer can be selected as the CPU clock (ICLK) or SysTick timer clock (SYSTICCLK). See section 8, Clock Generation Circuit and reference 1.
Page 51 RA0E1 User's Manual 2. CPU 2.7.3.1 Starting connection while in low power mode When starting a SWD connection from an OCD emulator, the MCU must be in Normal or Sleep mode. If the MCU is in Software Standby or Snooze mode, the OCD emulator can cause the MCU to hang.
Page 52: References
RA0E1 User's Manual 2. CPU 2. Set up SWJ-DP to access the DAP bus. In the setup, the OCD emulator must assert CDBGPWRUPREQ in SWJ-DP Control Status Register, then wait until CDBGPWRUPACK in the same register is asserted. 3. Set up the APB-AP to access OCDREG. The APB-AP is connected to the DAP bus port 1.
Page 53: Operating Modes
RA0E1 User's Manual 3. Operating Modes Operating Modes Overview The MCU starts in single-chip mode and the on-chip flash is enabled when a reset is released. In single-chip mode, all I/O pins are available for use as input or output port, inputs or outputs for peripheral functions, or as interrupt inputs.
Page 54: Address Space
RA0E1 User's Manual 4. Address Space Address Space Address Space The MCU supports a 4-GB linear address space ranging from 0x0000_0000 to 0xFFFF_FFFF that can contain both program and data. Figure 4.1 shows the memory map of a 64-KB/32-KB flash product.
Page 55: Resets
RA0E1 User's Manual 5. Resets Resets Overview The MCU provides 7 resets. Table 5.1 lists the reset names and sources. Table 5.1 Reset names and sources Reset name Source RES pin reset Voltage input to the RES pin is driven low...
Page 56 RA0E1 User's Manual 5. Resets Table 5.3 Module-related registers initialized by each reset source (1 of 2) Reset source Voltage Independent Power-on monitor 0 watchdog Registers to be initialized RES pin reset reset reset timer reset Registers related to the IWDTRR, IWDTSR ✓...
Page 57: Register Descriptions
RA0E1 User's Manual 5. Resets Table 5.4 States of SOSC when a reset occurs Reset source Other SOSC Enable or disable Initialized to disable Continue with the state that was selected before the reset occurred Drive capability Initialized to low power mode 1...
Page 58: Porsr : Power-On Reset Status Register
RA0E1 User's Manual 5. Resets This register is cleared after it is read, in addition to when a reset occurs as described in Table 5.2. 5.2.2 PORSR : Power-On Reset Status Register Base address: SYSC = 0x4001_E000 Offset address: 0x0831...
Page 59: Voltage Monitor Reset
RA0E1 User's Manual 5. Resets Supply voltage (VCC) det0 Lower limit voltage for guaranteed operation Wait for oscillation Wait for oscillation accuracy stabilization accuracy stabilization HOCO Starting oscillation Starting oscillation is specified by software is specified by software MOSC (when X1 oscillation is selected)
Page 60: Independent Watchdog Timer Reset
RA0E1 User's Manual 5. Resets Delay for Delay for LVD reset Delay for detection detection processing time detection Supply voltage (VCC) det1* det0* Lower limit of operating voltage Time LVD1MKR.MK LVD1CR.LVD1EN LVD1SR.MON Clear RESF.LVIRF LVD reset signal Cleared by software...
Page 61: Option-Setting Memory
RA0E1 User's Manual 6. Option-Setting Memory Option-Setting Memory Overview The option-setting memory determines the state of the MCU after a reset. The Option-setting memory is allocated to the configuration setting area and the program flash area of the flash memory. The available methods of setting are different for the two areas.
Page 62 RA0E1 User's Manual 6. Option-Setting Memory Symbol Function IWDTCKS[3:0] IWDT Clock Frequency Division Ratio Select 0x0: × 1 0x2: × 1/16 0x3: × 1/32 0x4: × 1/64 0xF: × 1/128 0x5: × 1/256 Others: Setting prohibited IWDTRPES[1:0] IWDT Window End Position Select...
Page 63: Ofs1 : Option Function Select Register 1
RA0E1 User's Manual 6. Option-Setting Memory IWDTRPSS[1:0] bits (IWDT Window Start Position Select) The IWDTRPSS[1:0] bits specify the position where the window for the down counter starts as 25%, 50%, 75%, or 100% of the counted value. The point at which counting starts is 100% and the point at which an underflow occurs is 0%. The interval between the window starts and ends positions becomes the period in which a refresh is possible.
Page 64 RA0E1 User's Manual 6. Option-Setting Memory Symbol Function 14:12 HOCOFRQ1[2:0] HOCO Frequency Setting 1 0 0 0: 24 MHz 0 1 0: 32 MHz Others: Setting prohibited PORTSELB P206/RES Terminal Selection 0: Port (P206) 1: RES input (internal pull-up register is always active.)
Page 65: Aws : Access Window Setting Register
RA0E1 User's Manual 6. Option-Setting Memory Starting address of a protected region Bit position FRPS[5:0] Bit filed Ending address of a protected region Bit position FRPE[5:0] Bit filed Figure 6.2 Starting and ending address of a protected 6.2.3 AWS : Access Window Setting Register...
Page 66: Osis : Ocd/Serial Programmer Id Setting Register
RA0E1 User's Manual 6. Option-Setting Memory The access window is specified in both the FAWS[10:0] bits and the FAWE[10:0] bits. The settings for the FAWS[10:0] and FAWE[10:0] bits are as follows: FAWE[10:0] = FAWS[10:0]: The P/E command is allowed to execute in the full program flash area.
Page 67: Setting Option-Setting Memory
RA0E1 User's Manual 6. Option-Setting Memory Table 6.2 Specifications for ID code protection Operating mode on Operations on connection to programmer or on- boot up ID code State of protection chip debugger On-chip debug mode 0xFF, …, 0xFF (all bytes are...
Page 68: Usage Notes
RA0E1 User's Manual 6. Option-Setting Memory Usage Notes 6.4.1 Data for Programming Reserved Areas and Reserved Bits in the Option-Setting Memory When reserved areas and reserved bits in the option-setting memory are within the scope of programming, write 1 to all bits of reserved areas and all reserved bits.
Page 69: Low Voltage Detection (Lvd)
RA0E1 User's Manual 7. Low Voltage Detection (LVD) Low Voltage Detection (LVD) Overview The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The detection level can be selected by register settings. The LVD module consists of two separate voltage level detectors (LVD0, LVD1). LVD0 and LVD1 measure the voltage level input to the VCC pin.
Page 70: Register Descriptions
RA0E1 User's Manual 7. Low Voltage Detection (LVD) Internal reset signal 0 Internal reset signal det0 Internal reset signal 1 Reference voltage source OFS1.VDSEL0[2:0] bits OFS1.LVDAS bit Note: For details of OFS1.LVDAS and OFS1.VDSEL0[2:0], see section 6, Option-Setting Memory. Figure 7.1...
Page 71: Lvd1Mkr : Voltage Monitor 1 Circuit Mask Register
RA0E1 User's Manual 7. Low Voltage Detection (LVD) Symbol Function LVD1V[4:0] *1 *2 Voltage Detection 1 Level Select 0x0E: V det1_0 0x0F: V det1_1 0x10: V det1_2 0x11: V det1_3 0x12: V det1_4 0x13: V det1_5 0x14: V det1_6 0x15: V...
Page 72: Lvd1Sr : Voltage Monitor 1 Circuit Status Register
RA0E1 User's Manual 7. Low Voltage Detection (LVD) Note: Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register. 7.2.3 LVD1SR : Voltage Monitor 1 Circuit Status Register Base address: SYSC = 0x4001_E000 Offset address: 0x0843 Bit position: Bit field: —...
Page 73: Interrupt And Reset From Voltage Monitor 1
RA0E1 User's Manual 7. Low Voltage Detection (LVD) LVD reset Delay for Delay for Delay for processing time detection detection detection Supply voltage (VCC) det0 Lower limit of operating voltage Time Clear RESF.LVIRF LVD reset signal Cleared by software POR reset signal...
Page 74: Event Link Controller (Elc) Output
RA0E1 User's Manual 7. Low Voltage Detection (LVD) LVD reset Delay for Delay for Delay for processing time detection detection detection Supply voltage (VCC) det1 det0 Lower limit of operating voltage POR, Time LVD1MKR.MK LVD1CR.LVD1EN LVD1SR.MON Voltage monitor 1 interrupt request(LVD_LVD1) LVD1SR.DET...
Page 75: Clock Generation Circuit
RA0E1 User's Manual 8. Clock Generation Circuit Clock Generation Circuit Overview The MCU provides a clock generation circuit. Table 8.1 Table 8.2 list the clock generation circuit specifications. Figure Figure 8.2 show a block diagram, and Table 8.3 lists the I/O pins.
Page 76 RA0E1 User's Manual 8. Clock Generation Circuit CKSEL FOCOSCR DIV[2:0] CKSEL MOSCDIV CKSEL FMAINSCR ICLKSCR Frequency FOCO divider FMAIN Main clock System clock (ICLK) Main clock To CPU, Flash, SRAM, Flash-IF oscillator X2/EXCLK 1/16 CKSEL Peripheral module clock (PCLKB) FSUBSCR...
Page 77: Register Descriptions
RA0E1 User's Manual 8. Clock Generation Circuit CKSEL FOCOSCR DIV[2:0] CKSEL MOSCDIV XTSEL CKSEL FMAINSCR ICLKSCR Frequency FOCO divider FMAIN Main clock System clock (ICLK) Main clock X1/XCIN oscillator To CPU, Flash, SRAM, Flash-IF 1/16 CKSEL Peripheral module clock (PCLKB)
Page 78 RA0E1 User's Manual 8. Clock Generation Circuit Symbol Function MODRV Main Clock Oscillator Drive Capability Switching 0: 1 MHz to 10 MHz 1: 10 MHz to 20 MHz SODRV[1:0] Sub-Clock Oscillator Drive Capability Switching 0 0: Low Power Mode 1...
Page 79: Somrg : Sub-Clock Oscillator Margin Check Register
RA0E1 User's Manual 8. Clock Generation Circuit 8.2.2 SOMRG : Sub-clock Oscillator Margin Check Register Base address: SYSC = 0x4001_E000 Offset address: 0x0803 Bit position: Bit field: — — — — — — SOSCMRG[1:0] Value after reset: Symbol Function SOSCMRG[1:0]...
Page 80: Fmainscr : Fmain Clock Source Control Register
RA0E1 User's Manual 8. Clock Generation Circuit 8.2.4 FMAINSCR : FMAIN Clock Source Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x0821 Bit position: CKSE Bit field: — — — — — — CKST Value after reset: Symbol Function...
Page 81: Iclkscr : Iclk Clock Source Control Register
RA0E1 User's Manual 8. Clock Generation Circuit ● Sub System clock (FSUB) Writing to FSUBSCR.CKSEL is prohibited while MCU is under the following conditions: 1. ICLKSCR.CKSEL = 1 2. ICLKSCR.CKST = 1 The bit selects one of the following sources: ●...
Page 82: Sosccr : Sub-Clock Oscillator Control Register
RA0E1 User's Manual 8. Clock Generation Circuit Symbol Function MOSTP Main Clock Oscillator Stop 0: Operate the main clock oscillator 1: Stop the main clock oscillator — These bits are read as 0. The write value should be 0. Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Page 83: Lococr : Low-Speed On-Chip Oscillator Control Register
RA0E1 User's Manual 8. Clock Generation Circuit ● Confirm that the sub-clock oscillator is stable when stopping the sub-clock oscillator ● Regardless of whether the sub-clock oscillator is selected as the system clock, confirm that the sub-clock oscillation is stable before executing a WFI instruction to place the MCU in Software Standby mode ●...
Page 84: Hococr : High-Speed On-Chip Oscillator Control Register
RA0E1 User's Manual 8. Clock Generation Circuit 8.2.10 HOCOCR : High-speed On-chip Oscillator Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x0808 Bit position: HCST Bit field: — — — — — — — Value after reset: Symbol Function...
Page 85: Ostc : Oscillation Stabilization Time Counter Status Register
RA0E1 User's Manual 8. Clock Generation Circuit Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register. The MOCOCR register controls the MOCO clock. MCSTP bit (MOCO Stop) The MCSTP bit starts or stops the MOCO clock.
Page 86 RA0E1 User's Manual 8. Clock Generation Circuit Release from the Software Standby mode Voltage waveform on the X1 pin Figure 8.3 Initial oscillation image Note: : MOSC clock oscillation frequency MOSC This register indicates the counter value by the MOSC clock oscillation stabilization time counter.
Page 87: Osts : Oscillation Stabilization Time Select Register
RA0E1 User's Manual 8. Clock Generation Circuit 8.2.13 OSTS : Oscillation Stabilization Time Select Register Base address: SYSC = 0x4001_E000 Offset address: 0x0811 Bit position: Bit field: — — — — — OSTSB[2:0] Value after reset: Symbol Function OSTSB[2:0] Selection of the Oscillation Stabilization Time...
Page 88: Oscsf : Oscillation Stabilization Flag Register
RA0E1 User's Manual 8. Clock Generation Circuit 8.2.14 OSCSF : Oscillation Stabilization Flag Register Base address: SYSC = 0x4001_E000 Offset address: 0x0812 Bit position: HOCO Bit field: — — — — — — — Value after reset: Symbol Function HOCOSF...
Page 89: Mocodiv : Middle-Speed On-Chip Oscillator Frequency Select Register
RA0E1 User's Manual 8. Clock Generation Circuit Note 1. Setting prohibited when OFS1.HOCOFRQ1[2:0] = 000b 8.2.16 MOCODIV : Middle-speed On-chip Oscillator Frequency Select Register Base address: SYSC = 0x4001_E000 Offset address: 0x0819 Bit position: Bit field: — — — —...
Page 90: Osmc : Subsystem Clock Supply Mode Control Register
RA0E1 User's Manual 8. Clock Generation Circuit Table 8.7 Example division ratio for the MOSC clock (MOSCDIV) = 20 MHz DIV[2:0] Selected division ratio for the MOSC clock MOSC 000b × 1/1 20 MHz MOSC 001b × 1/2 10 MHz...
Page 91: Liotrm : Low-Speed On-Chip Oscillator Trimming Register
RA0E1 User's Manual 8. Clock Generation Circuit Symbol Function CCS[2:0] Clock Out Divide Select 0 0 0: value after reset FMAIN (When CKS0.CSEL = 0) FSUB (When CKS0.CSEL = 1) 0 0 1: FMAIN × 1/2 (When CKS0.CSEL = 0) FSUB ×...
Page 92: Miotrm : Middle-Speed On-Chip Oscillator Trimming Register
RA0E1 User's Manual 8. Clock Generation Circuit Symbol Function LIOTRM[7:0] LOCO User Trimming 0x00: Minimum speed 0x01: ⋮ ⋮ 0x80: Initial value ⋮ ⋮ 0xFE: 0xFF: Maximum speed Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Page 93: Hiotrm : High-Speed On-Chip Oscillator Trimming Register
RA0E1 User's Manual 8. Clock Generation Circuit 8.2.22 HIOTRM : High-speed On-chip Oscillator Trimming Register Base address: FLCN = 0x407E_C000 Offset address: 0x0200 Bit position: Bit field: — — HIOTRM[5:0] Value after reset: Symbol Function HIOTRM[5:0] HOCO User Trimming 0x00: Minimum speed ⋮...
Page 94: External Clock Input
RA0E1 User's Manual 8. Clock Generation Circuit Figure 8.5 Equivalent circuit of the crystal resonator 8.3.2 External Clock Input Figure 8.6 shows an example of connecting an external clock input. To operate the oscillator with an external clock signal, set the CMC.MOSEL bit to 11b. The X1 pin can be used as an I/O port.
Page 95: Internal Clock
RA0E1 User's Manual 8. Clock Generation Circuit XCIN XCOUT Figure 8.7 Connection example of 32.768-kHz crystal resonator Figure 8.8 shows an equivalent circuit for the 32.768-kHz crystal resonator. XCIN XCOUT Figure 8.8 Equivalent circuit for the 32.768-kHz crystal resonator Internal Clock Clock sources for the internal clock signals include: ●...
Page 96 RA0E1 User's Manual 8. Clock Generation Circuit ● DIV[2:0] in HOCODIV ● DIV[2:0] in MOCODIV ● DIV[2:0] in MOSCDIV ● CKSEL in FOCOSCR ● CKSEL in FMAINSCR ● CKSEL in FSUBSCR ● CKSEL in ICLKSCR When the clock source of ICLK is being switched, the duration of ICLK clock cycle become longer during the clock source transition period.
Page 97: Rtc-Dedicated Clock (Rtcclk)
RA0E1 User's Manual 8. Clock Generation Circuit Source A (Low speed) CKSEL Source A (Low speed) Source A (Low speed) CKST Source B (High speed) Source A (Low speed) Selected clock Clock source A Clock source B Figure 8.10 Timing of clock source switching ●...
Page 98: Usage Notes
RA0E1 User's Manual 8. Clock Generation Circuit ● DIV[2:0] in MOSCDIV ● CKSEL in FOCOSCR ● CKSEL in FMAINSCR ● CKSEL in FSUBSCR Usage Notes 8.6.1 Register Access 1. Do not write to registers listed in this section for the following condition: [Registers] ●...
Page 99: Notes On Resonator Connect Pin
RA0E1 User's Manual 8. Clock Generation Circuit Prohibited Signal A Signal B Prohibited Figure 8.11 Signal routing in board design for oscillation circuit 8.6.5 Notes on Resonator Connect Pin When the main clock is not used (CMC.MOSEL[0] bit is 0), the X1 and X2 pins can be used as general ports. When the main clock is External clock input mode (CMC.MOSEL[1:0] bits are 11b), the X1 pin can be used as general ports.
Page 100: Low Power Modes
RA0E1 User's Manual 9. Low Power Modes Low Power Modes Overview The MCU provides several functions for reducing power consumption, such as setting clock dividers, stopping modules, selecting power control mode in normal mode, and transitioning to low power modes.
Page 101 RA0E1 User's Manual 9. Low Power Modes Table 9.2 Operating conditions of each low power mode (2 of 2) Item Sleep mode Software Standby mode Snooze mode Serial Array Unit (SAU0) Selectable Stop (Retained) Selectable Serial Array Unit (SAU1) Selectable...
Page 102: Register Descriptions
RA0E1 User's Manual 9. Low Power Modes SBYCR.SSBY = 0 Reset state Sleep mode WFI instruction RES pin = High All interrupts Snooze mode Interrupt Snooze request Snooze end condition Normal mode (program execution state) WFI instruction SBYCR.SSBY = 1...
Page 103: Mstpcra : Module Stop Control Register A
RA0E1 User's Manual 9. Low Power Modes Symbol Function SSBY Software Standby Mode Select 0: Sleep mode 1: Software Standby mode. Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register. FLSTP bit (Flash Mode in Sleep Mode or in Snooze Mode) When the FLSTP bit is set to 1, power consumption can be reduced because Flash stops during Sleep mode or Snooze mode.
Page 104: Mstpcrb : Module Stop Control Register B
RA0E1 User's Manual 9. Low Power Modes 9.2.3 MSTPCRB : Module Stop Control Register B Base address: MSTP = 0x4004_7000 Offset address: 0x0000 Bit position: Bit field: — — — — — — — — — — — — —...
Page 105: Mstpcrd : Module Stop Control Register D
RA0E1 User's Manual 9. Low Power Modes Symbol Function MSTPC1 Cyclic Redundancy Check Calculator Module Stop Target module: CRC 0: Cancel the module-stop state 1: Enter the module-stop state 13:2 — These bits are read as 1. The write value should be 1.
Page 106: Flmode : Flash Operating Mode Control Register
RA0E1 User's Manual 9. Low Power Modes 9.2.6 FLMODE : Flash Operating Mode Control Register Base address: FLCN = 0x407E_C000 Offset address: 0x020A Bit position: Bit field: MODE[1:0] — — — — — — Value after reset: Symbol Function —...
Page 107: Psmcr : Power Save Memory Control Register
RA0E1 User's Manual 9. Low Power Modes Symbol Function FLMWEN Control of Flash Operation Mode Select Register 0: Rewriting the FLMODE register is disabled 1: Rewriting the FLMODE register is enabled — These bits are read as 0. The write value should be 0.
Page 108: Syocdcr : System Control Ocd Control Register
RA0E1 User's Manual 9. Low Power Modes 9.2.9 SYOCDCR : System Control OCD Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x0863 Bit position: DBGE Bit field: — — — — — — — Value after reset: Symbol Function —...
Page 109 RA0E1 User's Manual 9. Low Power Modes Table 9.7 Available oscillators in each mode Oscillator High-speed on-chip Middle-speed on-chip Low-speed on-chip Main clock Sub-clock Mode oscillator oscillator oscillator oscillator oscillator High-speed Available Available Available Available Available Middle-speed Available Available Available...
Page 110: Operating Range
RA0E1 User's Manual 9. Low Power Modes (Operation is now in High-speed mode) Note: There is an automatic wait time. ● Middle-speed to High-speed: 225 clocks ● Low-speed to Middle_speed: 10 clocks ● Middle-speed to Low-speed: 10 clocks ● High-speed to Middle-speed: 30clocks ●...
Page 111 RA0E1 User's Manual 9. Low Power Modes VCC[V] VCC[V] Except P/E 0.032768 ICLK[MHz] 0.032768 ICLK[MHz] Figure 9.3 Operating voltages and frequencies in Middle-speed mode Low-speed mode The maximum operating frequency during a flash read is 2 MHz for ICLK. The operating voltage range during a flash read is 1.6 to 5.5 V.
Page 112: Sleep Mode
RA0E1 User's Manual 9. Low Power Modes VCC[V] VCC[V] Except P/E is prohibited ICLK[MHz] ICLK[MHz] Figure 9.5 Operating voltages and frequencies in Subosc-speed mode Sleep Mode 9.6.1 Transitioning to Sleep Mode When a WFI instruction is executed while SBYCR.SSBY bit is 0, the MCU enters Sleep mode. In this mode, the CPU stops operating but the contents of its internal registers are retained.
Page 113: Software Standby Mode
RA0E1 User's Manual 9. Low Power Modes Note: For details on proper setting of the interrupts, see section 11, Interrupt Controller Unit (ICU). Software Standby Mode 9.7.1 Transition to Software Standby Mode When a WFI instruction is executed while SBYCR.SSBY bit is 1, the MCU enters Software Standby mode. In this mode, the CPU, most of the on-chip peripheral functions and oscillators stop.
Page 114: Example Of Software Standby Mode Application
RA0E1 User's Manual 9. Low Power Modes Software Standby mode is canceled by an internal reset generated by an IWDT underflow and the MCU starts the reset exception handling. However, IWDT stops in Software Standby mode and an internal reset for canceling Software Standby mode is not generated in the following condition: ●...
Page 115: Canceling Snooze Mode
RA0E1 User's Manual 9. Low Power Modes Snooze Control Circuit Clock request signal SAU0 Snooze request signal Clock request signal Control DTC activation request DTC transfer complete Figure 9.7 Snooze mode entry configuration Table 9.8 shows the Snooze requests to switch the MCU from Software Standby mode to Snooze mode. To use the listed Snooze requests as a trigger to switch to Snooze mode.
Page 116: Low Power Modes
RA0E1 User's Manual 9. Low Power Modes Trigger Interrupt instruction detection request High Standby cancel signal High Snooze reqest signal Software Standby Normal mode Low power mode mode Snooze mode Normal mode Oscillation Oscillator Oscillates stopped Oscillates for system clock Wait for oscillation accuracy stabilization Note 1.
Page 117: Usage Notes
RA0E1 User's Manual 9. Low Power Modes Start Snooze mode setting Setting for DTC in Snooze mode MSTPCRA.MSTPC22 = 0 Cancel module-stop state of DTC DTC setting See Section 14.5 DTC Setting Procedure Setting for Snooze cancel Enable event as the source of canceling SBYEDCRy.xxxED = 1...
Page 118: I/O Port Pin States
RA0E1 User's Manual 9. Low Power Modes ● Flash P/E mode, data flash P/E mode Valid setting for the clock-related registers Table 9.9 shows the valid settings for the clock-related registers in each operating power control mode. Do not write any value other than the valid setting, otherwise it is ignored.
Page 119: Timing Of Wfi Instruction
RA0E1 User's Manual 9. Low Power Modes 9.9.6 Timing of WFI Instruction It is possible for the WFI instruction to be executed before I/O register write is completed, in which case operation might not be as intended. This can happen if the WFI is placed immediately after a write to an I/O register. To avoid this problem, read back the register that was written to confirm that the write completed.
Page 120: Register Write Protection
RA0E1 User's Manual 10. Register Write Protection Register Write Protection 10.1 Overview The register write protection function protects important registers from being overwritten due to software errors. The registers to be protected are set with the Protect Register (PRCR). Table 10.1 lists the association between the bits in the PRCR register and the registers to be protected.
Page 121: Interrupt Controller Unit (Icu)
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Interrupt Controller Unit (ICU) 11.1 Overview The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector Interrupt Controller (NVIC), and the Data Transfer Controller (DTC) modules. The ICU also controls non-maskable interrupts.
Page 122: Register Descriptions
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Interrupt Controller SRAM Parity error IWDT underflow/refresh error Clock Clock recovery request generation circuit Voltage monitor 1 interrupt Low voltage detection Clock recovery Clock recovery enable level determination NMI pin Detection SBYEDCRn...
Page 123: Nmisr : Non-Maskable Interrupt Status Register
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Symbol Function IRQMD[1:0] IRQi Detection Sense Select 0 0: Falling edge 0 1: Rising edge 1 0: Rising and falling edges 1 1: Setting prohibited — These bits are read as 0. The write value should be 0.
Page 124: Nmier : Non-Maskable Interrupt Enable Register
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) When 1 is written to the NMICLR.IWDTCLR bit. LVD1ST flag (Voltage Monitor 1 Interrupt Status Flag) The LVD1ST flag indicates a request for voltage monitor 1 interrupt. It is read-only and cleared by the NMICLR.LVDCLR bit.
Page 125: Nmiclr : Non-Maskable Interrupt Status Clear Register
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) IWDTEN bit (IWDT Underflow/Refresh Error Interrupt Enable) The IWDTEN bit enables IWDT underflow/refresh error interrupt as an NMI trigger. LVD1EN bit (Voltage Monitor 1 Interrupt Enable) The LVD1EN bit enables voltage monitor 1 interrupt as an NMI trigger.
Page 126: Nmicr : Nmi Pin Interrupt Control Register
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) 11.2.5 NMICR : NMI Pin Interrupt Control Register Base address: ICU = 0x4000_6000 Offset address: 0x0100 Bit position: NMIM Bit field: — — — — — — — Value after reset: Symbol...
Page 127: Dtcenst1 : Dtc Enable Status Register 1
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Symbol Function 19:18 ST18 to ST19 DTC Enable Status by Event Number i The suffix number of each bit symbol corresponds to the DTC vector number i. 0: DTC Disable by Event number i...
Page 128: Dtcenset0 : Dtc Enable Set Register 0
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Symbol Function 31:10 — These bits are read as 0. STi bits (DTC Enable Status by Event Number i) (i = 32 to 38, 40 to 41) The STi bit indicates whether the corresponding event is disabled or enabled as a DTC activation factor. This register is read-only and is set by the DTCENSETn.SETi bit and cleared by the DTCENCLRn.CLRi bit.
Page 129: Dtcenset1 : Dtc Enable Set Register 1
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Symbol Function 23:22 SET22 to SET23 DTC Enable Set by Event Number i The suffix number of each bit symbol corresponds to the DTC vector number i. 0: No effect 1: DTC Enable by Event number i 26:24 —...
Page 130: Dtcenclr0 : Dtc Enable Clear Register 0
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) 11.2.10 DTCENCLR0 : DTC Enable Clear Register 0 Base address: ICU = 0x4000_6000 Offset address: 0x0320 Bit position: Bit field: CLR31 CLR30 CLR29 CLR28 CLR27 — — — CLR23 CLR22 — —...
Page 131: Dtcenclr1 : Dtc Enable Clear Register 1
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) 11.2.11 DTCENCLR1 : DTC Enable Clear Register 1 Base address: ICU = 0x4000_6000 Offset address: 0x0324 Bit position: Bit field: — — — — — — — — — — — —...
Page 132: Intflag1 : Interrupt Request Flag Monitor Register 1
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) IFi flags (Interrupt Request Flag Monitor) (i = 0 to 7, 10 to 31) The IFi flag indicates whether an interrupt request or a DTC request of the event i is being accepted by the ICU or not. This register is read-only.
Page 133: Sbyedcr0 : Software Standby/Snooze End Control Register 0
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) – MRB.DISEL = 0 and Remaining transfer operations = 0 – MRB.DISEL = 1 ● When 1 is written to the DTCENSETn.SETi bit or DTCENCLRn.CLRi bit. To clear the interrupt request flag, write 1 to the DTCENSETn.SETi bit or DTCENCLRn.CLRi bit.
Page 134: Sbyedcr1 : Software Standby/Snooze End Control Register 1
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Symbol Function UART0RXED UART0 Reception Transfer End Interrupt Snooze Mode Returns Enable 0: Snooze Mode returns by UART0 reception transfer end interrupt disabled 1: Snooze Mode returns by UART0 reception transfer end interrupt enabled 30:28 —...
Page 135: Vector Table
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Symbol Function RTCED RTC Interrupt Software Standby/Snooze Mode Returns Enable 0: Software Standby/Snooze Mode returns by RTC interrupt disabled 1: Software Standby/Snooze Mode returns by RTC interrupt enabled ITLED Interval Signal of 32-bit Interval Timer Interrupt Software Standby/Snooze Mode Returns...
Page 136: Interrupt Vector Table
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) 11.3.1 Interrupt Vector Table Table 11.3 describes the interrupt vector table. The interrupt vector addresses conform to the NVIC specifications. Table 11.3 Interrupt vector table (1 of 3) Exception Vector number number...
Page 137 RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Table 11.3 Interrupt vector table (2 of 3) Exception Vector number number offset Source Description 0x088 SAU0_UART_TXI0/ UART0 transmission transfer end or buffer empty interrupt/SPI00 SAU0_SPI_TXRXI00/ transfer end or buffer empty interrupt/IIC00 transfer end...
Page 138: Event Number
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Table 11.3 Interrupt vector table (3 of 3) Exception Vector number number offset Source Description 0x118 Reserved Reserved 0x11C Reserved Reserved 0x120 Reserved Reserved 0x124 Reserved Reserved 0x128 Reserved Reserved 0x12C Reserved...
Page 139: Interrupt Operation
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) Table 11.5 Event table (2 of 2) Interrupt Canceling request Connect to Canceling Software Event number source Name NVIC Invoke DTC Snooze Standby ELC_SWEVT0 ✓ — — ✓ ELC_SWEVT1 ✓ — —...
Page 140: Interrupt Setting Procedure
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) ● Edges (falling edge, rising edge, or rising and falling edges) Set the IRQCRi.IRQMD[1:0] bits to select the detection mode for the IRQi pins. For interrupt sources associated with peripheral modules, see Table 11.3.
Page 141: External Pin Interrupts
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) 11.5.4.1 CPU interrupt request When DTCENSTn.STi = 0, the interrupt is output to the NVIC. 11.5.4.2 DTC activation When DTCENSTn.STi = 1, the interrupt is output to the DTC. Use the following procedure: 1.
Page 142: Return From Low Power Modes
RA0E1 User's Manual 11. Interrupt Controller Unit (ICU) 3. Enable the non-maskable interrupt by writing 1 to the associated bit in the Non-Maskable Interrupt Enable Register (NMIER). After 1 is written to the NMIER register, subsequent write access to the NMIEN bit in NMIER is ignored. An NMI cannot be disabled when enabled, except by a reset.
Page 143: Buses
RA0E1 User's Manual 12. Buses Buses 12.1 Overview Table 12.1 lists the bus specifications, Figure 12.1 shows the bus configuration, and Table 12.2 lists the addresses assigned for each bus. Table 12.1 Bus specifications Bus type Description Main bus System bus (CPU) ●...
Page 144: Description Of Buses
RA0E1 User's Manual 12. Buses Table 12.2 Addresses assigned for each bus (2 of 2) Address Area 0x4001_A000 to 0x4001_FFFF Internal peripheral bus 1 Peripheral I/O registers 0x4004_0000 to 0x400B_FFFF Internal peripheral bus 3 0x400C_0000 to 0x400D_FFFF Internal peripheral bus 7...
Page 145: Register Descriptions
RA0E1 User's Manual 12. Buses instruction such as STREX instruction always gets a failed status. When an exclusive write operation is performed by the CPU, the main bus always writes the data successfully. 12.3 Register Descriptions 12.3.1 BUSMCNTx : Master Bus Control Register x (x = SYS, DMA)
Page 146: Busnerrstat : Bus Error Status Register N (N = 3, 4)
RA0E1 User's Manual 12. Buses The value of the BUSnERRADD.BERAD[31:0] bits (n = 3, 4) is valid only when the BUSnERRSTAT.ERRSTAT flag (n = 3, 4) is set to 1. 12.3.3 BUSnERRSTAT : BUS Error Status Register n (n = 3, 4)
Page 147: Conditions For Issuing Illegal Address Access Errors
RA0E1 User's Manual 12. Buses 12.4.3 Conditions for issuing illegal Address Access Errors Table 12.4 lists the address spaces for each bus that issue illegal address access errors. Table 12.4 Conditions leading to illegal address access errors Main buses System...
Page 148: Flash Read Protection (Frp)
RA0E1 User's Manual 13. Flash Read Protection (FRP) Flash Read Protection (FRP) 13.1 Overview The MCU incorporates the Flash Read Protection (FRP) function with one secure region that include the code flash. The secure region can be protected from read accesses. Any program cannot read data in a protected region.
Page 149: Usage Notes
RA0E1 User's Manual 13. Flash Read Protection (FRP) Flash read protection setting Memory Memory Non-secure data Code flash ending address defined by FRPS bits Protected Secure data region starting address defined by FRPS bits Non-secure data Note: Any program cannot read secure data (Protected region).
Page 150: Data Transfer Controller (Dtc)
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Data Transfer Controller (DTC) 14.1 Overview A Data Transfer Controller (DTC) module is provided for transferring data when activated by an interrupt request. Table 14.1 lists the DTC specifications and Figure 14.1 shows DTC block diagram.
Page 151: Register Descriptions
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Non-maskable interrupt request NVIC interrupt request Interrupt controller Register Vector number control Activation Activation request control DTC response Bus interface DTCCR Snooze control DTCVBR response signals control DTCST DTC_ DTCEND DTCSTS System...
Page 152: Mrb : Dtc Mode Register B
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Symbol Function — The read values are undefined. The write value should be 0. — SM[1:0] Transfer Source Address Addressing Mode — 0 0: Address in the SAR register is fixed (write-back to SAR is skipped.) 0 1: Address in the SAR register is fixed (write-back to SAR is skipped.)
Page 153: Sar : Dtc Transfer Source Register
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Symbol Function CHNS DTC Chain Transfer Select — 0: Chain transfer is continuous. 1: Chain transfer occurs only when the transfer counter changes from 1 to 0 or 1 to CRAH. CHNE DTC Chain Transfer Enable —...
Page 154: Dar : Dtc Transfer Destination Register
RA0E1 User's Manual 14. Data Transfer Controller (DTC) 14.2.4 DAR : DTC Transfer Destination Register Base address: DTCVBR Offset address: 0x0008 + 0x4 × Vector number (Inaccessible directly from the CPU. See section 14.3.1. Allocating Transfer Information and DTC Vector...
Page 155: Crb : Dtc Transfer Count Register B
RA0E1 User's Manual 14. Data Transfer Controller (DTC) 14.2.6 CRB : DTC Transfer Count Register B Base address: DTCVBR Offset address: 0x000C + 0x4 × Vector number (Inaccessible directly from the CPU. See section 14.3.1. Allocating Transfer Information and DTC Vector...
Page 156: Dtcst : Dtc Module Start Register
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Symbol Function 31:0 DTC Vector Base Address Set the DTC vector base address. The lower 10 bits should be 0. The DTCVBR sets the base address for calculating the DTC vector table address, which can be set in the range of 0x0000_0000 to 0xFFFF_FFFF (4 GB) in 1-KB units.
Page 157: Activation Sources
RA0E1 User's Manual 14. Data Transfer Controller (DTC) VECN[7:0] bits (DTC-Activating Vector Number Monitoring) While transfer by the DTC is in progress, the VECN[7:0] bits indicate the vector number associated with the activation source for the transfer. The value read from the VECN[7:0] bits is valid if the ACT flag is 1, indicating a DTC transfer in progress, and invalid if the ACT flag is 0, indicating no DTC transfer is in progress.
Page 158 RA0E1 User's Manual 14. Data Transfer Controller (DTC) Upper: DTCVBR DTC vector table Lower: Vector number × 4 Transfer information (1) DTC vector address Transfer information (1) start address Transfer information (2) start address Transfer information (2) +4(n - 1)
Page 159: Operation
RA0E1 User's Manual 14. Data Transfer Controller (DTC) 14.4 Operation The DTC transfers data according to the transfer information. Storage of the transfer information in the SRAM area is required before a DTC operation. When the DTC is activated, it reads the DTC vector associated with the vector number.
Page 160 RA0E1 User's Manual 14. Data Transfer Controller (DTC) Start Match and DTCCR.RRS = 1 Compare vector numbers. Match? Mismatch or DTCCR.RRS = 0 Read DTC vector Next transfer Read transfer information Update transfer information start address MRB.CHNE = 1 MRB.CHNS = 0 MRA.MD[1:0] = 01b...
Page 161: Transfer Information Read Skip Function
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Table 14.3 Chain transfer conditions First transfer Second transfer CHNE CHNS DISEL CHNE CHNS DISEL *1 *2 *1 *2 Transfer counter Transfer counter DTC transfer — Other than (1 → 0) —...
Page 162: Normal Transfer Mode
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Table 14.4 Transfer information write-back skip conditions and applicable registers MRA.SM[1:0] bits MRB.DM[1:0] bits SAR register DAR register Skip Skip Skip Write-back Write-back Skip Write-back Write-back 14.4.3 Normal Transfer Mode The normal transfer mode allows a 1-byte (8 bit), 1-halfword (16 bit), 1-word (32 bit) data transfer on a single activation source.
Page 163: Repeat Transfer Mode
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area Transfer 6 times Data 1 Data 1 (transfer 1 data unit per event) Data 2 Data 2 Data 3 Data 3 Data 4 Data 4...
Page 164: Block Transfer Mode
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area (set to repeat area) Transfer 8 times Data 1 Data 1 (transfer 1 data unit per event) Data 2 Data 2 Data 3 Data 3...
Page 165: Chain Transfer
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area (set to block area) First block Transfer Block area nth block Figure 14.7 Memory map of block transfer mode 14.4.6 Chain Transfer Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single activation source. If the MRB.CHNE is set to 1 and CHNS to 0, an interrupt request to the CPU is not generated on completion of the specified...
Page 166: Operation Timing
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Data area Transfer source data (1) Transfer information DTC vector table allocated in the SRAM Transfer destination data (1) DTC vector Transfer information address CHNE = 1 Transfer information start address Transfer information...
Page 167 RA0E1 User's Manual 14. Data Transfer Controller (DTC) System clock ICU.INTFLAGn.IFi DTC activation request DTC access Vector read Transfer Data Transfer information read transfer information write Figure 14.9 Example 1 of DTC operation timing in normal transfer and repeat transfer modes System clock ICU.INTFLAGn.IFi...
Page 168: Execution Cycles Of Dtc
RA0E1 User's Manual 14. Data Transfer Controller (DTC) System clock ICU.INTFLAGn.IFi DTC activation request DTC access Data Data Vector read Transfer Transfer Transfer Transfer transfer information read transfer information information information write read write Figure 14.11 Example 3 of DTC operation timing for chain transfer System clock ICU.INTFLAGn.IFi...
Page 169: Dtc Bus Mastership Release Timing
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Table 14.8 Execution cycles of DTC P: Block size (initial settings of CRAH and CRAL) Cv: Cycles for access to vector transfer information storage destination Ci: Cycles for access to transfer information storage destination address...
Page 170: Examples Of Dtc Usage
RA0E1 User's Manual 14. Data Transfer Controller (DTC) 14.6 Examples of DTC Usage 14.6.1 Normal Transfer This section provides an example of DTC usage and its application when consecutively capturing A/D conversion results 40 times. Transfer information settings In the MRA register, select a fixed source address (MRA.SM[1:0] = 00b), normal transfer mode (MRA.MD[1:0] = 00b), and halfword-sized transfer (MRA.SZ[1:0] = 01b).
Page 171: Chain Transfer When Counter = 0
RA0E1 User's Manual 14. Data Transfer Controller (DTC) 5. Set the DAR register to the address of the data table in the SRAM area where to store the A/D conversion result. 6. Set the CRA registers to the size of the data table. The CRB register can be set to any value.
Page 172 RA0E1 User's Manual 14. Data Transfer Controller (DTC) (b) CRA register = 0x0200 (512) times. (c) MRB.CHNE bit = 1 (chain transfer is enabled). (d) MRB.CHNS bit = 1 (chain transfer is performed only when the transfer counter is 0).
Page 173: Interrupt
RA0E1 User's Manual 14. Data Transfer Controller (DTC) Source(1) (Fixed) Input circuit ⋮ Normal Transfer information allocated in (0x8000) Destination(1) the on-chip memory space Transfer (0x81FF) ⋮ Input buffer (0x8200) (0x83FF) First data transfer Transfer Information (TI) Destination(3) upper 8bits...
Page 174: Usage Notes
RA0E1 User's Manual 14. Data Transfer Controller (DTC) DTC transfer ends. While the MSTPCRA.MSTPA22 bit is 1, accessing the DTC registers is prohibited. Writing 0 to the MSTPCRA.MSTPA22 bit releases the DTC from the module-stop state. Software Standby Mode Use the settings described in section 9.7.1.
Page 175: Event Link Controller (Elc)
RA0E1 User's Manual 15. Event Link Controller (ELC) Event Link Controller (ELC) 15.1 Overview The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to connect them to different modules, allowing direct link between the modules without CPU intervention.
Page 176: Register Descriptions
RA0E1 User's Manual 15. Event Link Controller (ELC) 15.2 Register Descriptions 15.2.1 ELCR : Event Link Controller Register Base address: ELC = 0x4004_1000 Offset address: 0x0000 Bit position: ELCO Bit field: — — — — — — — Value after reset:...
Page 177: Elsrn : Event Link Setting Register N (N = 23 To 28)
RA0E1 User's Manual 15. Event Link Controller (ELC) WI bit (ELSEGR Register Write Disable) The ELSEGR register can only be written to when the write value to the WI bit is 0. This bit is read as 1. To write the WE or SEG bit, the WI bit must be written to 0 at the same time.
Page 178: Operation
RA0E1 User's Manual 15. Event Link Controller (ELC) Table 15.3 Association between event signal names set in ELSRn.ELS[5:0] bits and signal numbers (2 of 2) Event number Interrupt request source Name Description 0x08 TML32 TML32_ITL0 32 bit interval timer0 compare-match...
Page 179: Example Of Procedure For Linking Events
RA0E1 User's Manual 15. Event Link Controller (ELC) 15.3.3 Example of Procedure for Linking Events To link events: 1. Set the operation of the module for which an event is to be linked. 2. Set the appropriate ELSRn.ELS[5:0] bits for the module to be linked.
Page 180: Link Availability In Sleep, Software Standby, And Snooze Mode
RA0E1 User's Manual 15. Event Link Controller (ELC) Delay time Event source Event destination Module A Module B Figure 15.2 ELC delay time Table 15.5 ELC delay time Module Event Name Delay time ADC12 ELC_AD 4 or 5 cycles of ICLK after an event input to ELC, the hardware trigger is detected in ADC12.
Page 181: I/O Ports
RA0E1 User's Manual 16. I/O Ports I/O Ports 16.1 Overview The I/O port pins operate as general I/O port pins, I/O pins for peripheral modules, interrupt input pins, analog I/O, port group function for the ELC. All pins operate as input pins immediately after a reset, and pin functions are switched by register settings. The I/O ports and peripheral modules for each pin are specified in the associated registers.
Page 182: Register Descriptions
RA0E1 User's Manual 16. I/O Ports Table 16.1 I/O port specifications (2 of 2) Package Package Package Package Number of Number of Number of Number of Port 32 pins pins 24 pins pins 20 pins pins 16 pins pins Port 1...
Page 183: Pdrm : Pmn Direction Register (M = 0 To 9, N = 00 To 15)
RA0E1 User's Manual 16. I/O Ports ● PODR2: P2n Output Data Register (n = 01, 06 to 08, 12, 13) ● PODR3: P3n Output Data Register (n = 00) ● PODR4: P4n Output Data Register (n = 07) ● PODR9: P9n Output Data Register (n = 13, 14) PODRn bits (Pmn Output Data) The PODRn bits hold data to be output from the general I/O pins.
Page 184: Pidrm : Pmn State Register (M = 0 To 9, N = 00 To 15)
RA0E1 User's Manual 16. I/O Ports 16.2.3 PIDRm : Pmn State Register (m = 0 to 9, n = 00 to 15) Base address: PORTm = 0x400A_0000 + 0x20 × m (m = 0 to 9) Offset address: 0x0006 Bit position:...
Page 185: Posrm : Pmn Output Set Register (M = 0 To 9, N = 00 To 15)
RA0E1 User's Manual 16. I/O Ports ● PORR0: P0n Output Reset Register (n = 08 to 15) ● PORR1: P1n Output Reset Register (n = 00 to 03, 08 to 10, 12) ● PORR2: P2n Output Reset Register (n = 01, 06 to 08, 12, 13) ●...
Page 186: Eorrm : Pmn Event Output Reset Register (M = 1 To 2, N = 00 To 15)
RA0E1 User's Manual 16. I/O Ports 16.2.6 EORRm : Pmn Event Output Reset Register (m = 1 to 2, n = 00 to 15) Base address: PORTm = 0x400A_0000 + 0x20 × m (m = 1 to 2) Offset address: 0x000C...
Page 187: Pmnpfs_A : Port Mn Pin Function Select Register (M = 1 To 4, N = 00 To 15)
RA0E1 User's Manual 16. I/O Ports Note: When EORRm.EORRn = 1 or EOSRm.EOSRn = 1, writing is prohibited to PODRm.PODRn, PORRm.PORRn and POSRm.POSRn. 16.2.8 PmnPFS_A : Port mn Pin Function Select Register (m = 1 to 4, n = 00 to 15) Base address: PFS_A = 0x400A_0200 Offset address: 0x0000 + 0x20 ×...
Page 188 RA0E1 User's Manual 16. I/O Ports PODR bit (Pmn Output Data), PIDR bit (Pmn State), PDR bit (Pmn Direction) The PDR, PIDR, and PODR bits serve the same function as the PDRm, PIDRm, PODRm. When these bits are read, the PDRm, PIDRm, PODRm value is read.
Page 189: P0Npfs_A : Port 0N Pin Function Select Register (N = 08 To 15)
RA0E1 User's Manual 16. I/O Ports When N-ch open drain output is selected for serial communications with an external device operating at a different voltage or an input port is not used, low power consumption can be achieved by setting the corresponding PMC bit to 1.
Page 190: Pwpr : Write-Protect Register
RA0E1 User's Manual 16. I/O Ports Symbol Function PODR P9n Output Data 0: Low output 1: High output PIDR P9n State 0: Low level 1: High level P9n Direction 0: Input (functions as an input pin) 1: Output (functions as an output pin) —...
Page 191: Port Function Select
RA0E1 User's Manual 16. I/O Ports ● Pmn Input Data bit (PIDRn), which indicates the pin states ● Pmn Output Set bit (POSRn), which indicates the output value when a software write occurs ● Pmn Output Reset bit (PORRn), which indicates the output value when a software write occurs ●...
Page 192: Handling Of Unused Pins
RA0E1 User's Manual 16. I/O Ports EOSR PODR EORR ELC_PORTn Figure 16.2 Event ports output data Note: When linking the PORT with events, do not turn off ELC setting or rewrite PODR register with CPU while ELC event is being transferred.
Page 193: Usage Notes
RA0E1 User's Manual 16. I/O Ports 16.5 Usage Notes 16.5.1 Procedure for Specifying the Pin Functions To specify the I/O pin functions: 1. Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register.
Page 194 RA0E1 User's Manual 16. I/O Ports Table 16.5 Examples of register settings for port and alternate functions (1/6) Function Used Pin Name Function Name PSEL[2:0] ISEL PODR P008 P008 Input 000b — Output 000b — AN002 Analog Input 000b —...
Page 195 RA0E1 User's Manual 16. I/O Ports Table 16.6 Examples of register settings for port and alternate functions (2/6) (1 of 3) Function Used Pin Name Function Name PSEL[2:0] ISEL NCODR PMC PODR P100 P100 Input 000b Output 000b N-ch open drain output...
Page 196 RA0E1 User's Manual 16. I/O Ports Table 16.6 Examples of register settings for port and alternate functions (2/6) (2 of 3) Function Used Pin Name Function Name PSEL[2:0] ISEL NCODR PMC PODR P103 P103 Input 000b Output 000b N-ch open drain output...
Page 197 RA0E1 User's Manual 16. I/O Ports Table 16.6 Examples of register settings for port and alternate functions (2/6) (3 of 3) Function Used Pin Name Function Name PSEL[2:0] ISEL NCODR PMC PODR P112 P112 Input 000b Output 000b N-ch open drain output...
Page 198 RA0E1 User's Manual 16. I/O Ports Table 16.8 Examples of register settings for port and alternate functions (4/6) (2 of 2) Function Used Pin Name Function Name PSEL[2:0] ISEL NCODR PMC PODR P208 P208 Input 000b Output 000b N-ch open drain output...
Page 199: Notes On Communications With Devices Operating At A Different Voltage (1.8 V, 2.5 V, Or 3 V) By Switching I/O Buffers
RA0E1 User's Manual 16. I/O Ports Table 16.9 Examples of register settings for port and alternate functions (5/6) (2 of 2) Function Used Function Name Name SOSEL MOSEL[1:0] XTSEL PSEL[2:0] ISEL NCODR PMC PODR P214 P214 Input — — —...
Page 200: Restriction On P206 Usage
RA0E1 User's Manual 16. I/O Ports Procedure for setting output pins of UART0 to UART2, UARTA0, SPI00, SPI01, and SPI20 for use with the N-ch open-drain output mode 1. Pull up the input pin to be used to the voltage of the target device via an external resistor. The on-chip pull-up resistor cannot be used for this purpose.
Page 201 RA0E1 User's Manual 16. I/O Ports Table 16.11 Register settings for the pin function select configuration (PORT0) PSEL[2:0] settings P008 P009 P010 P011 P012 P013 P014 P015 000b P0n Output Data (initial) PMC bit ✓ (AN002) ✓ (AN003) ✓ (AN000/ ✓...
Page 202 RA0E1 User's Manual 16. I/O Ports Table 16.13 Register settings for the pin function select configuration (PORT2) (2 of 2) PSEL[2:0] settings P200 P201 P206 P207 P208 P212 P213 P214 P215 32-pin product ✓ ✓ ✓ ✓ ✓ ✓ ✓...
Page 203 RA0E1 User's Manual 16. I/O Ports Table 16.16 Register settings for the pin function select configuration (PORT9) (2 of 2) PSEL[2:0] settings P913 P914 NCODR bit — — PIM bit — — PCR bit — — 32-pin product ✓ ✓...
Page 204: Timer Array Unit (Tau)
RA0E1 User's Manual 17. Timer Array Unit (TAU) Timer Array Unit (TAU) 17.1 Overview The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more channels can be used to create a High functional timer.
Page 205 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.1 TAU functions Parameter Description Independent channel operation Interval timer Each timer of a unit can be used as a reference timer that generates an interrupt (TAU0_TMI0n) at fixed intervals. function...
Page 206 RA0E1 User's Manual 17. Timer Array Unit (TAU) Note 4. Timer array unit is used to check whether signals received in LIN-bus communication match the LIN-bus communication format. For details about setting up the operations used to implement the LIN-bus, see section 17.2.16.
Page 207 RA0E1 User's Manual 17. Timer Array Unit (TAU) Compare operation Timer input Interrupt signal (TAUm_TMImn) (TImn) Channel n (master) Edge detection Pulse width Output timing Compare operation Timer output Reset Channel p (slave) (TOmp) (Slave) (Master) Start (Master) Figure 17.9...
Page 208 RA0E1 User's Manual 17. Timer Array Unit (TAU) Timer clock select register 0 (TPS0) PRS3[1:0] PRS2[1:0] PRS1[3:0] PRS0[3:0] Prescaler PCLKB PCLKB/2 , PCLKB/2 PCLKB/2 PCLKB/2 , PCLKB/2 PCLKB/2 PCLKB/2 , PCLKB/2 PCLKB/2 , PCLKB/2 Selector Selector Timer input select register 1 (TIS1)
Page 209 RA0E1 User's Manual 17. Timer Array Unit (TAU) CK00 Output TCLK TO00 Timer controller controller CK01 Mode Timer input select selection Interrupt register 1 (TIS1) controller TAU0_TMI00 Edge TIS[1:0] (Timer interrupt) detection Timer counter register 00 (TCR00) TI00 Timer status...
Page 210 RA0E1 User's Manual 17. Timer Array Unit (TAU) Interrupt signal from the master channel CK00 Output TCLK TO0n Timer controller controller CK01 Mode selection Interrupt controller TAU0_TMI0n Edge (Timer interrupt) TI0n detection Timer counter register 0n (TCR0n) Timer status register 0n (TSR0n)
Page 211: Register Descriptions
RA0E1 User's Manual 17. Timer Array Unit (TAU) Interrupt signal from the master channel CK00 Output TCLK TO05 Timer controller controller CK01 Mode selection Interrupt Timer input select controller register 0 (TIS0) TAU0_TMI05 Edge (Timer interrupt) detection TIS[2:0] Timer status...
Page 212 RA0E1 User's Manual 17. Timer Array Unit (TAU) The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock. Whether the counter is incremented or decremented depends on the operation mode that is selected by the MD[2:0] bits and OPIRQ bit of timer mode register 0n (TMR0n) (see section 17.2.4.
Page 213: Tdr0N/Tdr01X/Tdr03X : Timer Data Register 0N (N = 0 To 7) (X = L, H)
RA0E1 User's Manual 17. Timer Array Unit (TAU) 17.2.2 TDR0n/TDR01x/TDR03x : Timer Data Register 0n (n = 0 to 7) (x = L, H) Base address: TAU = 0x400A_2600 Offset address: 0x0000 (TDR00) 0x0002 (TDR01/TDR01L) 0x0003 (TDR01H) 0x0004 (TDR02) 0x0006 (TDR03/TDR03L)
Page 214 RA0E1 User's Manual 17. Timer Array Unit (TAU) Symbol Function PRS0[3:0] *1 *3 *4 Selection of Operation Clock (CK00) 0x0: PCLKB 0x1: PCLKB/2 0x2: PCLKB/2 0x3: PCLKB/2 0x4: PCLKB/2 0x5: PCLKB/2 0x6: PCLKB/2 0x7: PCLKB/2 0x8: PCLKB/2 0x9: PCLKB/2 0xA: PCLKB/2...
Page 215 RA0E1 User's Manual 17. Timer Array Unit (TAU) is selected by using bits 7 to 4 of the TPS0 register. In addition, only for channels 1 and 3, CK02 and CK03 can be also selected. CK02 is selected by using bits 9 and 8 of the TPS0 register, and CK03 is selected by using bits 13 and 12 of the TPS0 register.
Page 216 RA0E1 User's Manual 17. Timer Array Unit (TAU) PRS2[1:0] bits (Selection of Operation Clock (CK02)) The input sources that can be selected with the PRS2[1:0] bits are shown in Table 17.5. Table 17.5 Selection of operation clock (PRS2[1:0]) Selection of operation clock (CK02)
Page 217: Tmr0N : Timer Mode Register 0N (N = 0, 2, 4, 5, 6, 7)
RA0E1 User's Manual 17. Timer Array Unit (TAU) 17.2.4 TMR0n : Timer Mode Register 0n (n = 0, 2, 4, 5, 6, 7) Base address: TAU = 0x400A_2600 Offset address: 0x0110 (TMR00) 0x0114 (TMR02) 0x0118 (TMR04) 0x011A (TMR05) 0x011C (TMR06)
Page 218 RA0E1 User's Manual 17. Timer Array Unit (TAU) TMR00, TMR05, TMR07: Fixed to 0 The TMR0n register sets an operation mode of channel n. This register is used to select the operation clock (f ), select the count clock, select the master or slave, select the 16-bit timer, specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
Page 219: Tmr0N : Timer Mode Register 0N (N = 1, 3)
RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.9 Operation mode selected with MD[2:0] bits (2 of 2) MD[2:0] Operation mode of channel n Corresponding function Count operation of TCR 100b One-count mode Delay counter or Counting down One-shot pulse output or...
Page 220 RA0E1 User's Manual 17. Timer Array Unit (TAU) Symbol Function CIS[1:0] Selection of TI0n Pin Input Valid Edge 0 0: Falling edge 0 1: Rising edge 1 0: Both edges (when low-level width is measured) Start trigger: Falling edge, Capture trigger: Rising edge...
Page 221: Tsr0N : Timer Status Register 0N (N = 0 To 7)
RA0E1 User's Manual 17. Timer Array Unit (TAU) STS[2:0] bits (Setting of Start Trigger or Capture Trigger of Channel n) These bits are used for setting the start trigger or capture trigger of channel n. SPLIT bit (Selection of 8 or 16-bit Timer Operation for Channels 1 and 3) This bit is used to select 8 or 16-bit timer operation for channels 1 and 3.
Page 222: Te0 : Timer Channel Enable Status Register 0
RA0E1 User's Manual 17. Timer Array Unit (TAU) 17.2.7 TE0 : Timer Channel Enable Status Register 0 Base address: TAU = 0x400A_2600 Offset address: 0x0130 Bit position: Bit field: — — — — TEH3 — TEH1 — TE[7:0] Value after reset:...
Page 223: Tt0 : Timer Channel Stop Register 0
RA0E1 User's Manual 17. Timer Array Unit (TAU) Symbol Function TSH3 Trigger to Enable Operation (Start Operation) of the Higher 8-bit Timer when Channel 3 is in the 8-bit Timer Mode 0: No trigger operation 1: The TE0.TEH3 bit is set to 1 and the count operation becomes enabled 15:12 —...
Page 224: Tis0 : Timer Input Select Register 0
RA0E1 User's Manual 17. Timer Array Unit (TAU) Symbol Function TTH3 Trigger to Stop Operation of the Higher 8-bit Timer when Channel 3 is in the 8-bit Timer Mode 0: No trigger operation 1: The TE0.TEH3 bit is cleared to 0 and the count operation is stopped 15:12 —...
Page 225: Toe0 : Timer Output Enable Register 0
RA0E1 User's Manual 17. Timer Array Unit (TAU) Note: When selecting the event input signal from ELC in this register, select PCLKB (undivided) as the operating clock in timer clock select register 0 (TPS0). 17.2.12 TOE0 : Timer Output Enable Register 0...
Page 226: Tol0 : Timer Output Level Register 0
RA0E1 User's Manual 17. Timer Array Unit (TAU) The TO0n bit on this register can be rewritten by software only when timer output is disabled (TOE0.TOE[n] = 0). When timer output is enabled (TOE0.TOE[n] = 1), rewriting this register by software is ignored, and the value is changed only by the timer operation.
Page 227: Isc : Input Switch Control Register
RA0E1 User's Manual 17. Timer Array Unit (TAU) The TOM0 register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.
Page 228: Tnfen : Tau Noise Filter Enable Register
RA0E1 User's Manual 17. Timer Array Unit (TAU) 17.2.17 TNFEN : TAU Noise Filter Enable Register Base address: PORGA = 0x400A_1000 Offset address: 0x0001 Bit position: TNFE TNFE TNFE TNFE TNFE TNFE TNFE TNFE Bit field: Value after reset: Symbol...
Page 229: Basic Rules Of Timer Array Unit
RA0E1 User's Manual 17. Timer Array Unit (TAU) ● Do not use the analog input (ex. AN0xx) For details, see the following sections. ● section 16.2.2. PDRm : Pmn Direction Register (m = 0 to 9, n = 00 to 15) ●...
Page 230: Basic Rules Of 8-Bit Timer Operation Function (Channels 1 And 3 Only)
RA0E1 User's Manual 17. Timer Array Unit (TAU) 12. To stop the channels in combination simultaneously, the channel stop trigger bit (TT0.TT[n]) of the channels in combination must be set at the same time. 13. CK02 and CK03 cannot be selected while channels are operating simultaneously, because the operating clocks of master channels and slave channels have to be synchronized.
Page 231: Operations Of Counters
RA0E1 User's Manual 17. Timer Array Unit (TAU) 6. For the higher 8 bits, the TS0.TSH1 and TSH3 bits are manipulated to start channel operation and the TT0.TTH1 and TTH3 bits are manipulated to stop channel operation. The channel state can be checked using the TE0.TEH1 and TEH3 bits.
Page 232 RA0E1 User's Manual 17. Timer Array Unit (TAU) PCLKB PCLKB/2 PCLKB/4 TCLK ( = f PCLKB/8 = CKmn) PCLKB/16 △: Rising edge of the count clock Note: ▲: Synchronization, increment or decrement of counter Note: PCLKB: CPU and peripheral hardware clock...
Page 233: Timing Of The Start Of Counting
RA0E1 User's Manual 17. Timer Array Unit (TAU) <1> Setting TS0.TS[n] bit to 1 enables the timer to be started and to become wait state for valid edge of input signal via the TI0n pin. <2> The rise of input signal via the TI0n pin is sampled by f <3>...
Page 234 RA0E1 User's Manual 17. Timer Array Unit (TAU) TCLK TSm.TS[n] (write) <1> TEm.TE[n] <2> Start trigger detection signal Initial TCRmn 0x0001 m - 1 0x0000 value TDRmn <4> <3> <5> TAUm_TMImn When TMRmn.OPIRQ = 1 setting Note: In the first cycle operation of count clock after writing the TSm.TS[n] bit, an error at a maximum of one clock is generated since count start delays until count clock has been generated.
Page 235 RA0E1 User's Manual 17. Timer Array Unit (TAU) TSm.TS[n] (write) <1> TEm.TE[n] <2> TImn input Edge detection Edge detection Count clock <4> Start trigger detection signal <3> <1> Initial m−1 m−2 TCRmn value <3> TDRmn Note: Figure 17.23 shows the timing when the noise filter is not used. By making the noise filter on-state, the edge detection becomes 2 f cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input.
Page 236 RA0E1 User's Manual 17. Timer Array Unit (TAU) TSm.TS[n] (write) <1> TEm.TE[n] <3> TImn input Edge detection Edge detection Rising edge <4> <5> Start trigger detection signal <3> <2> TCRmn 0x0000 0x0001 0x0000 m−1 0x0000 Initial value TDRmn 0x0001 TAUm_TMImn When TMRmn.OPIRQ = 1...
Page 237 RA0E1 User's Manual 17. Timer Array Unit (TAU) TCLK TSm.TS[n] (write) <1> TEm.TE[n] TImn input <3> Edge detection Rising edge <4> Start trigger detection signal <5> <2> TCRmn Initial value 0xFFFF TAUm_TMImn Start trigger input wait state Note: Figure 17.25 shows the timing when the noise filter is not used.
Page 238: Channel Output (To0N Pin) Control
RA0E1 User's Manual 17. Timer Array Unit (TAU) TCLK TSm.TS[n] (write) <1> TEm.TE[n] TImn input <3> Edge detection Edge detection Rising edge <4> <5> Falling edge Start trigger detection signal <2> Initial value TCRmn 0x0000 m−1 TDRmn 0x0000 TAUm_TMImn Note: Figure 17.26...
Page 239: To0N Pin Output Setting
RA0E1 User's Manual 17. Timer Array Unit (TAU) <2> When TOM0.TOM[n] = 1 (slave channel output mode), both TAU0_TMI0n (master channel timer interrupt) and TAU0_TMI0p (slave channel timer interrupt) are transmitted to the TO0 register. At this time, the TOL0 register becomes valid and the signals are controlled as follows: When TOL0.TOL[n] = 0: Positive logic output (TAU0_TMI0n →...
Page 240: Cautions On Channel Output Operation
RA0E1 User's Manual 17. Timer Array Unit (TAU) <4> The port is set to Peripheral output by the PSEL[2:0] bits of Port mn Pin Function Select Register (PmnPFS_A) (see section 16.2.8. PmnPFS_A : Port mn Pin Function Select Register (m = 1 to 4, n = 00 to 15), section 16.2.9.
Page 241 RA0E1 User's Manual 17. Timer Array Unit (TAU) Figure 17.30 shows the output state of the TO0p pin with PWM output (TOM0.TOM[p] = 1). TOEm.TOE[p] Active Active Active Default Hi-Z TOm.TO[p] bit = 0 state (default state: low) TOLm.TOL[p] bit = 0 (active-high) TOm.TO[p] bit = 1...
Page 242 RA0E1 User's Manual 17. Timer Array Unit (TAU) (1) Basic timing during operation TCLK TAUm_TMImn Master Internal reset channel signal TOmn pin/TOm.TO[n] Toggle Toggle Internal reset signal 1 clock delay TAUm_TMImp Slave channel Internal reset signal TOmp pin/TOm.TO[p] Reset (2) Timing during operation with the duty cycle set to 0%...
Page 243: Collective Manipulation Of To0.To[N] Bit
RA0E1 User's Manual 17. Timer Array Unit (TAU) 17.5.4 Collective Manipulation of TO0.TO[n] Bit In timer output register 0 (TO0), the setting bits for all the channels are located in one register in the same way as timer channel start register 0 (TS0). Therefore, the TO0.TO[n] bit of all the channels can be manipulated collectively.
Page 244: Timer Input (Ti0N) Control
RA0E1 User's Manual 17. Timer Array Unit (TAU) (a) When the TMRmn.OPIRQ bit is set to 1 TCRmn TEm.TE[n] TAUm_TMImn TOmn Count operation start (b) When the TMRmn.OPIRQ bit is set to 0 TCRmn TEm.TE[n] TAUm_TMImn TOmn Count operation start...
Page 245: Noise Filter
RA0E1 User's Manual 17. Timer Array Unit (TAU) 17.6.2 Noise Filter When the noise filter is disabled, the input signal is only synchronized with the operating clock (f ) for channel n. When the noise filter is enabled, after synchronization with the operating clock (f ) for channel n, whether the signal keeps the same value for two clock cycles is detected.
Page 246 RA0E1 User's Manual 17. Timer Array Unit (TAU) 0n (TMR0n) is 0 at this time,TAU0_TMI0n is not output and the output on TO0n is not toggled. If the TMR0n.OPIRQ bit of the TMR0n register is 1, TAU0_TMI0n is output and the output on TO0n is toggled.
Page 247 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.13 Example of TMR0n settings for operation as an interval timer or for square wave output Symbol Set value Function OPIRQ Setting of operation when counting is started 0: Neither generates TAU0_TMI0n nor inverts timer output when counting is started.
Page 248 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.16 Example of TOL0 settings for operation as an interval timer or for square wave output Symbol Set Value Function － (n = 0) Fixed to 0 (channels 0) TOL[n] (n = 1 to Control of timer output of channel n (channels 1 to 7) 0: Set this bit to 0 when TOM0.TOM[n] = 0 (master channel output mode).
Page 249: Operation As An External Event Counter
RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.18 Procedure for operations when the interval timer or square wave output function is to be used (2 of 2) Step Software operation Hardware state Operation <7> The TT0.TT[n] (TTH1, TTH3) bit is set to 1.
Page 250 RA0E1 User's Manual 17. Timer Array Unit (TAU) Figure 17.40 shows an example of basic timing during operation as an external event counter. TSm.TS[n] TEm.TE[n] TImn TCRmn 0x0000 TDRmn 0x0003 0x0002 TAUm_TMImn 4 events 4 events 3 events Note: m = 0, n = 0 to 7 Figure 17.40...
Page 251 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.19 Example of TMR0n settings in external event counter mode (2 of 2) Symbol Set value Function 15:14 CKS[1:0] Selection of the operating clock (f 0 0: Selects CK00 as the operating clock for channel n.
Page 252: Operation As A Frequency Divider (Channel 0 Of Unit 0 Only)
RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.24 Procedure for operations when the external event counter function is to be used (2 of 2) Step Software operation Hardware state Operation <4> Sets the TS0.TS[n] bit to 1. TE0.TE[n] = 1 and count operation starts.
Page 253 RA0E1 User's Manual 17. Timer Array Unit (TAU) TNFEN.TNFEN00 Noise Edge TI00 pin Timer counter Output filter detection TO00 pin register 00 (TCR00) controller Timer data TS0.TS[0] register 00 (TDR00) Figure 17.41 Block diagram for operation as a frequency divider Figure 17.42...
Page 254 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.25 Example of TMR00 settings for operation as a frequency divider (2 of 2) Symbol Set value Function Count clock selection 1: Selects the TI00 pin input valid edge. — Fixed to 0.
Page 255: Operation For Input Pulse Interval Measurement
RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.30 Procedure for operations when the frequency divider function is to be used (2 of 2) Step Software operation Hardware state Channel <3> Sets the corresponding bit of the TAU noise filter Channel stops operating.
Page 256 RA0E1 User's Manual 17. Timer Array Unit (TAU) When the channel start trigger bit (TS[n]) of timer channel start register 0 (TS0) is set to 1, the TCR0n register counts up from 0x0000 in synchronization with the count clock. When the TI0n pin input valid edge is detected, the count value of the TCR0n register is transferred (captured) to timer data register 0n (TDR0n) and, at the same time, the TCR0n register is cleared to 0x0000, and the TAU0_TMI0n is output.
Page 257 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.31 Example of TMR0n settings for operation for input pulse interval measurement Symbol Set value Function OPIRQ Setting of operation when counting is started 0: Neither generates TAU0_TMI0n nor inverts timer output when counting is started.
Page 258: Operation For Input Signal High- Or Low-Level Width Measurement
RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.34 Example of TOL0 settings for operation for input pulse interval measurement Symbol Set value Function — (n = 0) Fixed to 0 (channels 0) TOL[n] (n = 1 to Control of timer output of channel n (channels 1 to 7) 0: Set this bit to 0 when TOM0.TOM[n] = 0 (master channel output mode).
Page 259 RA0E1 User's Manual 17. Timer Array Unit (TAU) By starting counting at one edge of the TI0n pin input and capturing the number of counts at another edge, the signal width (high-level width or low-level width) of TI0n can be measured. The signal width of TI0n can be calculated by the following expression.
Page 260 RA0E1 User's Manual 17. Timer Array Unit (TAU) TSm.TS[n] TEm.TE[n] TImn 0xFFFF TCRmn 0x0000 TDRmn 0x0000 TAUm_TMImn TSRmn.OVF Note: m = 0, n = 0 to 7 Figure 17.46 Example of basic timing during operation for input signal high- or low-level width measurement Table 17.37...
Page 261 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.37 Example of TMR0n settings for operation for input signal high- or low-level width measurement (2 of 2) Symbol Set value Function 15:14 CKS[1:0] Selection of the operating clock (f 0 0: Selects CK00 as the operating clock for channel n.
Page 262: Operation As A Delay Counter
RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.42 Procedure for operations when the input signal high- or low-level width measurement function is to be used (2 of 2) Step Software operation Hardware state Operation <4> Sets TS0.TS[n] bit to 1.
Page 263 RA0E1 User's Manual 17. Timer Array Unit (TAU) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 TSm.TS[n] TNFEN.TNFENmn Timer data Interrupt signal Interrupt register mn (TDRmn) (TAUm_TMImn) controller Noise Edge TImn pin filter detection Note: m = 0, n = 0 to 7 Note 1.
Page 264 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.43 Example of TMR0n settings for operation as a delay counter (2 of 2) Symbol Set value Function — (n = 0, 5, 7) Fixed to 0 (channels 0, 5, 7)
Page 265: Simultaneous Channel Operation Function Of Timer Array Unit
RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.48 Procedure for operations when the delay counter function is to be used Step Software operation Hardware state TAU default — Power-off state setting (Clock supply is stopped and writing to each register is disabled.)
Page 266 RA0E1 User's Manual 17. Timer Array Unit (TAU) master channel) is detected. The output level of TO0p becomes active one count clock after generation of TAU0_TMI0n from the master channel, and inactive when TCR0p = 0x0000. Instead of using the TI0n pin input, a one-shot pulse can also be output using the software operation (TS0.TS[n] = 1) as a start trigger.
Page 267 RA0E1 User's Manual 17. Timer Array Unit (TAU) TSm.TS[n] TEm.TE[n] TImn Master 0xFFFF channel TCRmn 0x0000 TDRmn TOmn TAUm_TMImn TSm.TS[p] TEm.TE[p] 0xFFFF TCRmp Slave 0x0000 channel TDRmp TOmp TAUm_TMImp Note: m = 0, n = 0, 2, 4, 6 (master channel number) n <...
Page 268 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.49 Example of TMR0n settings for the master channel when the one-shot pulse output function is to be used (2 of 2) Symbol Set value Function — (n = 0) Fixed to 0 (channels 0)
Page 269 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.54 Example of TMR0p settings for the slave channel when the one-shot pulse output function is to be used (2 of 2) Symbol Set value Function — Fixed to 0 CIS[1:0]...
Page 270 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.59 Procedure for operations when the one-shot pulse output function is to be used (1 of 2) Step Software operation Hardware state TAU default — Power-off state setting (Clock supply is stopped and writing to each register is disabled.)
Page 271: Operation For The Pwm Function
RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.59 Procedure for operations when the one-shot pulse output function is to be used (2 of 2) Step Software operation Hardware state Operation <8> The TT0.TT[n] (master) and TT[p] (slave) bits are set TE0.TE[n], TE[p] = 0, and count operation stops.
Page 272 RA0E1 User's Manual 17. Timer Array Unit (TAU) In the 16-pin products, this function can be used by setting channels 0 and 2 as the master channel and the slave channel, respectively. Note: To rewrite both timer data register 0n (TDR0n) of the master channel and the TDR0p register of the slave channel, a write access is necessary two times.
Page 273 RA0E1 User's Manual 17. Timer Array Unit (TAU) TSm.TS[n] TEm.TE[n] 0xFFFF Master TCRmn channel 0x0000 TDRmn TOmn TAUm_TMImn TSm.TS[p] TEm.TE[p] 0xFFFF TCRmp Slave 0x0000 channel TDRmp TOmp TAUm_TMImp Note: m = 0 n = 0, 2, 4, 6 (master channel number) n <...
Page 274 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.60 Example of TMR0n settings for the master channel when the PWM function is to be used (2 of 2) Symbol Set value Function 15:14 CKS[1:0] Selection of the operating clock (f...
Page 275 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.65 Example of TMR0p settings for the slave channel when the PWM function is to be used (2 of 2) Symbol Set value Function Count clock selection 0: Selects operation clock (f —...
Page 276 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.70 Procedure for operations when the PWM function is to be used (2 of 2) Step Software operation Hardware state Channel <3> Sets timer mode register 0n, 0p (TMR0n, TMR0p) of Channel stops operating.
Page 277: Operation For The Multiple Pwm Output Function
RA0E1 User's Manual 17. Timer Array Unit (TAU) 17.8.3 Operation for the Multiple PWM Output Function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
Page 278 RA0E1 User's Manual 17. Timer Array Unit (TAU) Master channel (interval timer mode) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 Timer data Interrupt Interrupt signal TSm.TS[n] register mn (TDRmn) controller (TAUm_TMImn) Slave channel 1 (one-count mode) CKm1 Operation clock...
Page 279 RA0E1 User's Manual 17. Timer Array Unit (TAU) TSm.TS[n] TEm.TE[n] 0xFFFF Master TCRmn channel 0x0000 TDRmn TOmn TAUm_TMImn TSm.TS[p] TEm.TE[p] 0xFFFF TCRmp Slave 0x0000 channel 1 TDRmp TOmp TAUm_TMImp TSm.TS[q] TEm.TE[q] 0xFFFF TCRmq Slave 0x0000 channel 2 TDRmq TOmq TAUm_TMImq...
Page 280 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.71 Example of TMR0n settings for the master channel when the multiple PWM output function is to be used Symbol Set value Function OPIRQ Setting of operation when counting is started...
Page 281 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.76 Table 17.81 show register settings for the slave channel when the multiple PWM output function is to be used (for two types of PWM output). Table 17.76 Example of TMR0p settings for the slave channel when the multiple PWM output function is to be...
Page 282 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.77 Example of TMR0q settings for the slave channel when the multiple PWM output function is to be used (for two types of PWM output) (2 of 2) Symbol Set value Function —...
Page 283 RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.82 Procedure for operations when the multiple PWM output function is to be used (for two types of PWM output) (1 of 2) Step Software operation Hardware state TAU default —...
Page 284: Usage Notes
RA0E1 User's Manual 17. Timer Array Unit (TAU) Table 17.82 Procedure for operations when the multiple PWM output function is to be used (for two types of PWM output) (2 of 2) Step Software operation Hardware state Operation <7> The TT0.TT[n] bit (master), TT[p], and TT[q] (slave) TE0.TE[n], TE[p], TE[q] = 0, and count operation...
Page 285: Bit Interval Timer (Tml32)
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) 32-bit Interval Timer (TML32) 18.1 Overview The 32-bit interval timer is made up of four 8-bit interval timers (referred to as channels 0 to 3). Each is capable of operating independently and in that case they all have the same functions. Two 8-bit interval timer channels can be connected to operate as a 16-bit interval timer.
Page 286 RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) Table 18.1 Specifications of 32-bit interval timer operations Item Description Count source (operating clock) ● HOCO ● MOCO ● MOSC ● LOCO/SOSC (LOCO or SOSC) ● Event input from the ELC Capture clock (Selectable sources for ●...
Page 287: Register Descriptions
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) Note: In 16-bit counter mode, the counters in channels 0 and 1 are connected (ITL000 + ITL001) and the counters in channels 2 and 3 are connected (ITL012 + ITL013). In 32-bit counter mode, the counters in channels 0 to 3 are connected (ITL000 + ITL001 + ITL012 + ITL013).
Page 288: Itlctl0 : Interval Timer Control Register
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) 18.2.3 ITLCTL0 : Interval Timer Control Register Base address: TML32 = 0x400A_3800 Offset address: 0x0006 Bit position: Bit field: MD[1:0] — — Value after reset: Symbol Function 8-bit Counter Mode: ITL000 Count Enable...
Page 289: Itlcsel0 : Interval Timer Clock Select Register 0
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) EN3 bit (8-bit Counter Mode: ITL013 Count Enable) In 8-bit counter mode, writing 1 to this bit starts up-counting in the ITL013 counter and writing 0 stops it. In 16-bit counter mode, set this bit to 0.
Page 290: Itlfdiv00 : Interval Timer Frequency Division Register 0
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) 18.2.5 ITLFDIV00 : Interval Timer Frequency Division Register 0 Base address: TML32 = 0x400A_3800 Offset address: 0x0008 Bit position: Bit field: — FDIV1[2:0] — FDIV0[2:0] Value after reset: Symbol Function FDIV0[2:0] 8-bit Counter Mode: Counter Clock for ITL000...
Page 291: Itlfdiv01 : Interval Timer Frequency Division Register 1
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) 18.2.6 ITLFDIV01 : Interval Timer Frequency Division Register 1 Base address: TML32 = 0x400A_3800 Offset address: 0x0009 Bit position: Bit field: — FDIV3[2:0] — FDIV2[2:0] Value after reset: Symbol Function FDIV2[2:0] 8-bit Counter Mode: Counter Clock for ITL012...
Page 292: Itlcc0 : Interval Timer Capture Control Register 0
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) 18.2.7 ITLCC0 : Interval Timer Capture Control Register 0 Base address: TML32 = 0x400A_3800 Offset address: 0x000A Bit position: CAPE CAPF CAPC Bit field: CAPF CAPR — CTRS[1:0] Value after reset: Symbol...
Page 293 RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) Symbol Function ITF00 Compare Match Detection Flag for Channel 0 0: A compare match signal has not been detected in channel 0. 1: A compare match signal has been detected in channel 0.
Page 294: Itlmkf0 : Interval Timer Match Detection Mask Register
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) 18.2.9 ITLMKF0 : Interval Timer Match Detection Mask Register Base address: TML32 = 0x400A_3800 Offset address: 0x000C Bit position: MKF0 MKF0 MKF0 MKF0 MKF0 Bit field: — — — Value after reset:...
Page 295 RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) Table 18.4 Registers and settings used in 8-bit counter mode (2 of 2) Register name (symbol) Setting Interval timer control register 0 (ITLCTL0) Specify whether to start or stop counting in channel 0.
Page 296: Capture Mode Settings
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) Table 18.6 Registers and settings used in 32-bit counter mode (2 of 2) Register name (symbol) Setting Interval timer control register 0 (ITLCTL0) Specify whether to start or stop counting in channels 0 to Set to 0.
Page 297: Timer Operation
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) 18.3.3 Timer Operation The ITL0mn counter counts up cycles of the counting clock specified in the interval timer frequency division registers (ITLFDIV00 and ITLFDIV01). An interrupt request signal (TML32_ITL_OR) is generated on the counting of the next clock cycle after the value of the counter matches the comparison value.
Page 298: Interrupt
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) the counter clock. If a capture trigger is generated again within 2 cycles of the counter clock after an earlier capture trigger was generated, the ITLCC0.CAPF bit may not be set. Note 1. If the value of the ITLS0 register is other than 0x00, interrupt operation does not proceed even when the capture detection flag (ITF0C) is set to 1 because the interrupt request signal (TML32_ITL_OR) is kept at the high level.
Page 299 RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) Table 18.8 Interrupt sources in 8-bit, 16-bit, and 32-bit counter modes (2 of 2) Interrupt condition in 8-bit counter Interrupt condition in 16-bit counter Interrupt condition in 32-bit counter Interrupt source mode...
Page 300: Interval Timer Setting Procedures
RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) <12> The processing in response to the ITLS0.ITF00 flag being set to 1 is then executed. ITLS0.ITF01 flag ITLS0.ITF00 flag Interval detection interrupt signal (TML32_ITL_OR) Processing in response <1> Generation of <10> Checking <3>...
Page 301 RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) Table 18.10 Procedure for stopping the 32-bit interval timer Step Process Detail Stopping the 32-bit interval <1> Starting to stop the counter — timer <2> Set up masks for the ITLS0.ITF0i status flags.
Page 302 RA0E1 User's Manual 18. 32-bit Interval Timer (TML32) Table 18.12 Procedure for starting event input from the ELC Step Process Detail Starting event Input from <1> Start of the procedure for starting event input — the ELC from the ELC.
Page 303: Realtime Clock (Rtc)
RA0E1 User's Manual 19. Realtime Clock (RTC) Realtime Clock (RTC) This is the RTC_C version of the RTC peripheral module. RTC_C is referred to as RTC in this chapter. 19.1 Overview The realtime clock has the following features. Table 19.1...
Page 304: Register Descriptions
RA0E1 User's Manual 19. Realtime Clock (RTC) Note: The count of years, months, weeks, days, hours, minutes, and seconds can only proceed when the sub-clock oscillator (SOSC = 32.768 kHz) is selected as the operating clock of the realtime clock (RTCCLK). When the low-speed on-chip oscillator clock (LOCO = 32.768 kHz) is selected, only the fixed-cycle interrupt is available.
Page 305: Rtcc1 : Realtime Clock Control Register 1
RA0E1 User's Manual 19. Realtime Clock (RTC) RTC128EN bit (Selection of the operating clock for the realtime clock (RTCCLK)) ● Setting this bit to 1 enables the realtime clock to operate with the 128-Hz clock for lower-power operation. ● Time error correction cannot be used when the setting of this bit is 1.
Page 306: Sec : Second Count Register
RA0E1 User's Manual 19. Realtime Clock (RTC) So that the 16-bit internal counter continues to run, return the value of this bit to 0 on completion of reading or writing within one second. When reading or writing to the counter is required while generation of the alarm interrupt is enabled, first set the RTCC0.CT[2:0] bits to 010b (generating the constant-period interrupt once per 1 second).
Page 307: Min : Minute Count Register
RA0E1 User's Manual 19. Realtime Clock (RTC) Symbol Function — This bit is read as 0. The write value should be 0. Note: When reading from or writing to this register while the counter is in operation (RTCC0.RTCE = 1), follow the procedures described section 19.3.3.
Page 308: Day : Day Count Register
RA0E1 User's Manual 19. Realtime Clock (RTC) and then to the counter up to two cycles of RTCCLK later. Even if the minute count register overflows while this register is being written, this register ignores the overflow and is set to the value written. Specify a decimal value of 00 to 23, 01 to 12, or 21 to 32 by using BCD code according to the time system specified using the AMPM bit of the realtime clock control register 0 (RTCC0).
Page 309: Week : Day-Of-Week Count Register
RA0E1 User's Manual 19. Realtime Clock (RTC) Symbol Function DAY1[3:0] 1-day count Counts from 0 to 9 per day. When a carry is generated, 1 is added to the tens place. DAY10[1:0] 10-day count Counts from 0 to 3 once per carry from the ones place.
Page 310: Month : Month Count Register
RA0E1 User's Manual 19. Realtime Clock (RTC) 19.2.8 MONTH : Month Count Register Base address: RTC_C = 0x400A_2C00 Offset address: 0x0005 Bit position: MONT Bit field: — — — MONTH1[3:0] Value after reset: Symbol Function MONTH1[3:0] 1-month count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place.
Page 311: Subcud : Time Error Correction Register
RA0E1 User's Manual 19. Realtime Clock (RTC) 19.2.10 SUBCUD : Time Error Correction Register Base address: RTC_C = 0x400A_2C00 Offset address: 0x0007 Bit position: Bit field: F[5:0] Value after reset: Symbol Function F[5:0] Adjustment Value These bits specify the adjustment value from the prescaler.
Page 312: Alarmwm : Alarm Minute Register
RA0E1 User's Manual 19. Realtime Clock (RTC) 19.2.11 ALARMWM : Alarm Minute Register Base address: RTC_C = 0x400A_2C00 Offset address: 0x0008 Bit position: Bit field: — WM10[2:0] WM1[3:0] Value after reset: Symbol Function WM1[3:0] 1-digit minute setting Value for the ones place of minutes.
Page 313: Operation
RA0E1 User's Manual 19. Realtime Clock (RTC) Symbol Function Alarm enabled setting "Sunday" 0: Disable alarm settings for that day of the week 1: Enable alarm settings for that day of the week Alarm enabled setting "Monday" 0: Disable alarm settings for that day of the week 1: Enable alarm settings for that day of the week Alarm enabled setting "Tuesday"...
Page 314: Shifting To Sleep Or Software Standby Mode After Starting Operation
RA0E1 User's Manual 19. Realtime Clock (RTC) Start RTCC0.RTCE = 0 Stops counter operation. Setting OSMC.WUTMMCK0 Sets RTCCLK. Setting RTC128EN Selects SOSC or SOSC/256. Setting RTCC0.AMPM, CT[2:0] Selects 12- or 24-hour system and interrupt (RTC_ALM_OR_PRD). Setting SEC Sets second count register.
Page 315: Reading From And Writing To The Counters Of The Realtime Clock
RA0E1 User's Manual 19. Realtime Clock (RTC) ● Transition to Sleep or Software Standby mode when at least two counter clock cycles (RTCCLK) have elapsed after setting the RTCC0.RTCE bit to 1 (see Figure 19.3, Example 1). ● After setting the RTCC0.RTCE bit to 1 and then setting the RTCC1.RWAIT bit to 1, poll the RTCC1.RWST bit to check if it has become 1 yet.
Page 316 RA0E1 User's Manual 19. Realtime Clock (RTC) Start Stops SEC to YEAR counters. RTCC1.RWAIT = 1 Mode to read and write count values RTCC1..RWST = 1? Checks wait status of counter. Reading SEC Reads second count register. Reading MIN Reads minute count register.
Page 317: Setting Alarm By The Realtime Clock
RA0E1 User's Manual 19. Realtime Clock (RTC) Start Stops SEC to YEAR counters. RTCC1.RWAIT = 1 Mode to read and write count values Checks wait status of RTCC1.RWST = 1? counter. Writing SEC Writes second count register. Writing MIN Writes minute count register.
Page 318: Hz Output By The Realtime Clock
RA0E1 User's Manual 19. Realtime Clock (RTC) Start RTCC1.WALE = 0 Match operation of alarm is invalid. alarm match interrupts is valid. RTCC1.WALIE = 1 Setting ALARMWM Sets alarm minute register. Setting ALARMWH Sets alarm hour register. Setting ALARMWW Sets alarm day-of-week register.
Page 319 RA0E1 User's Manual 19. Realtime Clock (RTC) (When SUBCUD.DEV = 0) *1 *2 Correction value = Number of correction counts in 1 minute ÷ 3 = (Oscillation frequency ÷ Target frequency – 1) × 32768 × 60 ÷ 3 (When SUBCUD.DEV = 1)
Page 320 RA0E1 User's Manual 19. Realtime Clock (RTC) Figure 19.7 Operation for correction when the value of (SUBCUD.DEV, F6, F[5:0]) = 00101100b Correction example 2 Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm) [Measuring the oscillation frequency] R01UH1040EJ0110 Rev.1.10...
Page 321 RA0E1 User's Manual 19. Realtime Clock (RTC) To measure the oscillation frequency of each product, a signal at about 1 Hz can be output from the RTCOUT pin when the clock error correction register (SUBCUD) is set to its initial value (0x00).
Page 322 RA0E1 User's Manual 19. Realtime Clock (RTC) Figure 19.8 Operation for correction when the value of (SUBCUD.DEV, F6, F[5:0]) = 11101110b R01UH1040EJ0110 Rev.1.10 Page 322 of 734 Dec 13, 2024...
Page 323: Independent Watchdog Timer (Iwdt)
RA0E1 User's Manual 20. Independent Watchdog Timer (IWDT) Independent Watchdog Timer (IWDT) 20.1 Overview The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt or an underflow interrupt.
Page 324: Register Descriptions
RA0E1 User's Manual 20. Independent Watchdog Timer (IWDT) Interrupt request (IWDT_NMIUNDF) Interrupt control circuit IWDT reset output Reset control circuit Clock frequency divider IWDTCLK IWDTCLK IWDTCLK/16 IWDTCLK/32 IWDT control circuit 14-bit counter IWDTCLK/64 IWDTCLK/128 IWDTCLK/256 Option Function Select Register 0...
Page 325: Iwdtsr : Iwdt Status Register
RA0E1 User's Manual 20. Independent Watchdog Timer (IWDT) 20.2.2 IWDTSR : IWDT Status Register Base address: IWDT = 0x4004_4400 Offset address: 0x0004 Bit position: REFE UNDF Bit field: CNTVAL[13:0] Value after reset: Symbol Function 13:0 CNTVAL[13:0] Down-counter Value Value counted by the down-counter...
Page 326: Ofs0 : Option Function Select Register 0
RA0E1 User's Manual 20. Independent Watchdog Timer (IWDT) 20.2.3 OFS0 : Option Function Select Register 0 For information on the Option Function Select Register 0 (OFS0), see section 6.2.1. OFS0 : Option Function Select Register IWDTTOPS[1:0] bits (IWDT Timeout Period Select) The IWDTTOPS[1:0] bits select the timeout period, that is, the period until the down-counter underflows, from 128, 512, 1024, or 2048 cycles, taking the divided clock specified in the IWDTCKS[3:0] bits as 1 cycle.
Page 327 RA0E1 User's Manual 20. Independent Watchdog Timer (IWDT) IWDTRPES[1:0] bits (IWDT Window End Position Select) The IWDTRPES[1:0] bits specify the window end position that indicates the refresh-permitted period. 75%, 50%, 25%, or 0% of the timeout period can be selected for the window end position. Set the window end position to a value less than the window start position (window start position >...
Page 328: Operation
RA0E1 User's Manual 20. Independent Watchdog Timer (IWDT) IWDTSTPCTL bit (IWDT Stop Control) The IWDTSTPCTL bit selects whether to stop counting on transition to Sleep, Snooze, or Software Standby mode. 20.3 Operation 20.3.1 Auto Start Mode When the IWDT Start Mode Select bit (OFS0.IWDTSTRT) in the Option Function Select Register 0 is 0, auto start mode is selected, otherwise the IWDT is disabled.
Page 329: Refresh Operation
RA0E1 User's Manual 20. Independent Watchdog Timer (IWDT) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period Reset pin Refresh the counter Active: High Counting starts Counting starts Counting starts Counting starts Underflow Refresh error Refresh error...
Page 330: Status Flags
RA0E1 User's Manual 20. Independent Watchdog Timer (IWDT) ● 0x00 → 0x54 (a value other than 0xFF) ● 0x00 → 0xAA (0x00 and a value other than 0xFF) → 0xFF. After 0xFF is written to the IWDTRR register, refreshing the counter requires up to 4 cycles of the signal for counting (the IWDT Clock Frequency Division Ratio Select bits (OFS0.IWDTCKS[3:0]) to determine how many cycles of the...
Page 331: Reset Output
RA0E1 User's Manual 20. Independent Watchdog Timer (IWDT) 20.3.4 Reset Output When the IWDT Reset Interrupt Request Select bit (OFS0.IWDTRSTIRQS) in the Option Function Select Register 0 (OFS0) is set to 1, a reset signal is output when an underflow in the counter or a refresh error occurs. Counting down automatically starts after the reset output.
Page 332: Clock Division Ratio Setting
RA0E1 User's Manual 20. Independent Watchdog Timer (IWDT) 20.4.2 Clock Division Ratio Setting Satisfy the frequency of the peripheral module clock (PCLKB) ≥ 4 × (the frequency of the count clock source after division). R01UH1040EJ0110 Rev.1.10 Page 332 of 734...
Page 333: Serial Array Unit (Sau)
RA0E1 User's Manual 21. Serial Array Unit (SAU) Serial Array Unit (SAU) 21.1 Overview A Serial Array Unit (SAU) has up to two units. Unit0 has four channels and Unit1 has two channels. Each channel can achieve 3-wire serial(simplified SPI), UART or simplified IIC. And those function of each channel cannot assigned at the same time.
Page 334: Uart
RA0E1 User's Manual 21. Serial Array Unit (SAU) [Error detection flag] ● Overrun error In addition, simplified SPIs of following channels support the Snooze mode. In the Snooze mode, data can be received without CPU processing upon detecting SCK input in the Software Standby mode. The Snooze mode is only available in the following simplified SPIs, which support asynchronous reception.
Page 335: Simplified I 2 C
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.1.3 Simplified I This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master.
Page 336 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.3 Configuration of serial array (2 of 2) Item Configuration Control registers <Registers of unit setting block> ● Serial clock select register m (SPSm) ● Serial channel enable status register m (SEm) ●...
Page 337 RA0E1 User's Manual 21. Serial Array Unit (SAU) Serial clock select register 0 (SPS0) PRS1 PRS0 [3:0] [3:0] Prescaler PCLKB PCLKB/2 PCLKB/2 PCLKB/2 PCLKB/2 Selector Selector Serial data register 00 (SDR00) Channel 0 CK01 CK00 (Buffer register block) (Clock division setting block)
Page 338: Register Descriptions
RA0E1 User's Manual 21. Serial Array Unit (SAU) Serial clock select register 1 (SPS1) PRS0 PRS1 [3:0] [3:0] Prescaler PCLKB PCLKB/2 PCLKB/2 PCLKB/2 PCLKB/2 Selector Selector Serial data register 10 (SDR10) Channel 0 (Clock division setting block) CK11 CK10 (Buffer register block)
Page 339 RA0E1 User's Manual 21. Serial Array Unit (SAU) Symbol Function PRS0[3:0] Selection of Operation Clock (CKm0) 0x0: PCLKB 0x1: PCLKB/2 0x2: PCLKB/2 0x3: PCLKB/2 0x4: PCLKB/2 0x5: PCLKB/2 0x6: PCLKB/2 0x7: PCLKB/2 0x8: PCLKB/2 0x9: PCLKB/2 0xA: PCLKB/2 0xB: PCLKB/2...
Page 340: Smrmn : Serial Mode Register Mn (Mn = 00, 02, 10)
RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.4 Selection of operation clock (PRSk[3:0](k = 0, 1)) (2 of 2) Selection of operation clock (CKmk) (k = 0, 1) PCLKB = PCLKB = PCLKB = PCLKB = PCLKB =...
Page 341: Smrmn : Serial Mode Register Mn (Mn = 01, 03, 11)
RA0E1 User's Manual 21. Serial Array Unit (SAU) Rewriting the SMRmn register is prohibited when the register is in operation (when SEm.SE[n] = 1). However, the MD0 bit can be rewritten during operation. MD0 bit (Selection of Channel n Interrupt Source) For continuous transmission, set this bit to 1 and write the next transmit data when SDRmn data has run out.
Page 342: Scrm0 : Serial Communication Operation Setting Register M0 (M = 0, 1)
RA0E1 User's Manual 21. Serial Array Unit (SAU) Symbol Function Selection of Operation Clock (f ) of Channel n 0: Operation clock CKm0 set by the SPSm register 1: Operation clock CKm1 set by the SPSm register The SMRmn register is used to set an operation mode of channel n. It is also used to select an operation clock (f...
Page 343 RA0E1 User's Manual 21. Serial Array Unit (SAU) Symbol Function SLC[1:0] Setting of Stop Bit in UART Mode 0 0: No stop bit 0 1: Stop bit length = 1 bit 1 0: Stop bit length = 2 bits 1 1: Setting prohibited —...
Page 344: Scrm1 : Serial Communication Operation Setting Register M1 (M = 0, 1)
RA0E1 User's Manual 21. Serial Array Unit (SAU) Type 1 SCKp (DCP[1:0] = 00b) D2 D1 SIp input timing Type 2 SCKp (DCP[1:0] = 01b) D5 D4 D3 D2 SIp input timing Type 3 SCKp (DCP[1:0] = 10b) D7 D6 D5...
Page 345 RA0E1 User's Manual 21. Serial Array Unit (SAU) Symbol Function Mask Control of Error Interrupt Signal SAU0_UART_ERRI0 (m = 0), SAU1_UART_ERRI2 (m = 1) 0: Disables generation of error interrupt SAU0_UART_ERRI0 (m = 0), SAU1_UART_ERRI2 (m = 1) (SAUm_UART_RXIq is generated)
Page 346: Scr02 : Serial Communication Operation Setting Register 02
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.3.6 SCR02 : Serial Communication Operation Setting Register 02 Base address: SAU0 = 0x400A_2000 Offset address: 0x011C Bit position: Bit field: TRXE[1:0] DCP[1:0] — — PTC[1:0] — SLC[1:0] — — — Value after reset:...
Page 347: Scr03 : Serial Communication Operation Setting Register 03
RA0E1 User's Manual 21. Serial Array Unit (SAU) Set 1 bit (SLC[1:0] = 01b) during UART reception or in the simplified I C mode. Set no stop bit (SLC[1:0] = 00b) in the simplified SPI mode. Set 1 bit (SLC[1:0] = 01b) or 2 bits (SLC[1:0] = 10b) during UART transmission.
Page 348: Sdrmn : Serial Data Register Mn (Mn = 00, 01, 02, 03, 10, 11)
RA0E1 User's Manual 21. Serial Array Unit (SAU) Symbol Function 13:12 DCP[1:0] Selection of Data and Clock Phase in Simplified SPI Mode 0 0: Type1 (SCK: inverted, Input timing: rising edge) 0 1: Type2 (SCK: non-inverted, Input timing: falling edge)
Page 349: Sirmn : Serial Flag Clear Trigger Register Mn (Mn = 00, 02, 10)
RA0E1 User's Manual 21. Serial Array Unit (SAU) Symbol Function DAT[8:0] Data Buffer for Transmit and Receive 15:9 STCLK[6:0] Transfer Clock Setting by Dividing the Operation Clock 0x00: f /2 (Setting prohibited for UART and simplified I 0x01: f /4 (Setting prohibited for UART)
Page 350: Sirmn : Serial Flag Clear Trigger Register Mn (Mn = 01, 03, 11)
RA0E1 User's Manual 21. Serial Array Unit (SAU) Symbol Function OVCT Clear Trigger of Overrun Error Flag of Channel n 0: Not cleared 1: Clears the OVF bit of the SSRmn register to 0 PECT Clear Trigger of Parity Error Flag of Channel n 0: Not cleared 1: Clears the PEF bit of the SSRmn register to 0.
Page 351 RA0E1 User's Manual 21. Serial Array Unit (SAU) Symbol Function Parity or ACK Error Detection Flag of Channel n 0: No error occurs 1: Parity error occurs (during UART reception) or ACK is not detected (during I transmission) — These bits are read as 0.
Page 352: Ssrmn : Serial Status Register Mn (Mn = 01, 03, 11)
RA0E1 User's Manual 21. Serial Array Unit (SAU) TSF bit (Flag Indicating the State of Communications for Channel n) <Clearing condition> ● The ST[n] bit of the STm register is set to 1 (communication is stopped) or the SS[n] bit of the SSm register is set to 1 (communication is suspended).
Page 353: Ss0 : Serial Channel Start Register 0
RA0E1 User's Manual 21. Serial Array Unit (SAU) ● 1 is written to the PECT bit of the SIRmn register. <Setting condition> ● The parity of the transmit data and the parity bit do not match when UART reception ends (parity error).
Page 354: Ss1 : Serial Channel Start Register 1
RA0E1 User's Manual 21. Serial Array Unit (SAU) Note: For the UART reception, set the TRXE[0] bit of SCR0n register to 1, and then be sure to set the SS[n] bit to 1 after at least 4 f clock cycles have elapsed.
Page 355: St1 : Serial Channel Stop Register 1
RA0E1 User's Manual 21. Serial Array Unit (SAU) When 1 is written to a bit (ST[n]) of this register, the corresponding bit (SE[n]) of serial channel enable status register 0 (SE0) is cleared to 0 (operation is stopped). Because the ST[n] bit is a trigger bit, it is cleared immediately when SE0.SE[n] = 0.
Page 356: Se1 : Serial Channel Enable Status Register 1
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.3.18 SE1 : Serial Channel Enable Status Register 1 Base address: SAU1 = 0x400A_2200 Offset address: 0x0120 Bit position: Bit field: — — — — — — — — — — —...
Page 357: Soe1 : Serial Output Enable Register 1
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.3.20 SOE1 : Serial Output Enable Register 1 Base address: SAU1 = 0x400A_2200 Offset address: 0x012A Bit position: Bit field: — — — — — — — — — — — —...
Page 358: So1 : Serial Output Register 1
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.3.22 SO1 : Serial Output Register 1 Base address: SAU1 = 0x400A_2200 Offset address: 0x0128 Bit position: Bit field: — — — — — — CKO[1:0] — — — — — —...
Page 359: Sol1 : Serial Output Level Register 1
RA0E1 User's Manual 21. Serial Array Unit (SAU) When serial output is disabled (SOE0.SOE[n] = 0), the value of the SO0.SO[n] bit is output as is. Rewriting the SOL0 register is prohibited when the channel n is in operation (when SE0.SE[n] = 1).
Page 360: Ssc0 : Serial Standby Control Register 0
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.3.25 SSC0 : Serial Standby Control Register 0 Base address: SAU0 = 0x400A_2000 Offset address: 0x0138 Bit position: Bit field: — — — — — — — — — — — —...
Page 361: Isc : Input Switch Control Register
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.3.26 ISC : Input Switch Control Register Base address: PORGA = 0x400A_1000 Offset address: 0x0003 Bit position: SSIE0 Bit field: — — — — — ISC1 ISC0 Value after reset: Symbol Function...
Page 362: Ulbs : Uart Loopback Select Register
RA0E1 User's Manual 21. Serial Array Unit (SAU) Symbol Function SNFEN20 Use of Noise Filter of RXD2 Pin 0: Noise filter OFF 1: Noise filter ON — These bits are read as 0. The write value should be 0. Note 1. Be sure to clear bits [7:5], bit [3] and bit [1].
Page 363: Operation Stop Mode
RA0E1 User's Manual 21. Serial Array Unit (SAU) Symbol Function ULBS4 Selection of the UARTA Loopback Function 0: Inputs the states of the RXDA0 pin of serial interface UARTA0 to the reception shift register. 1: Loops back output from the transmission shift register to the reception shift register.
Page 364: Operation Of Simplified Spi
RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.9 Setting of serial output register m (SOm) when sopping the operation by channels Symbol Set value Function SO[n] Serial data output of channel n When using pins corresponding to each channel as port function pins, set the corresponding SO[n] bit to 1.
Page 365: Master Transmission
RA0E1 User's Manual 21. Serial Array Unit (SAU) ● Master transmission and reception (See section 21.5.3. Master Transmission and Reception.) ● Slave transmission (See section 21.5.4. Slave Transmission.) ● Slave reception (See section 21.5.5. Slave Reception.) ● Slave transmission and reception (See section 21.5.6.
Page 366 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.11 Example of serial mode register mn (SMRmn) contents for master transmission of simplified SPI (2 of 2) Symbol Set value Function Selection of start trigger source 0: Only software trigger is valid (selected for simplified SPI, UART transmission,...
Page 367: Operation Procedure
RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.14 Example of serial output register m (SOm) contents for master transmission of simplified Symbol Set value Function SO[n] Serial data output of channel n 0: Serial data output value is 0...
Page 368 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.17 Initial setting procedure for master transmission Step Process Detail Procedure for initial <1> Starting initial setting — setting of master <2> Setting the SPSm register Set the operation clock. transmission <3>...
Page 369 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.19 Procedure for resuming master transmission Step Process Detail Procedure for <1> Starting setting for resumption — resuming master <2> Wait until Slave is ready Wait until stop the communication target (slave) or transmission communication operation completed.
Page 370 RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting simplified SPI communication For the initial setting, see SAU initial setting (Select the transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag Setting transmit data...
Page 371 RA0E1 User's Manual 21. Serial Array Unit (SAU) <1> SSm.SS[n] STm.ST[n] <6> SEm.SE[n] SDRmn.DAT[7:0] Transmit data 2 Transmit data 3 Transmit data 1 SCKp pin Transmit data 1 Transmit data 2 Transmit data 3 SOp pin Shift register mn Shift operation...
Page 372: Master Reception
RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting setting <1> For the initial setting, see SAU initial setting (Select buffer empty interrupt) Set the data pointer for transmission and the number of data items. Clear communication end flag Setting transmit data...
Page 373: Register Setting
RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.20 Specification of master reception of simplified SPI Simplified SPI SPI00 SPI11 SPI20 Target channel Channel 0 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1 Pins used SCK00, SI00...
Page 374 RA0E1 User's Manual 21. Serial Array Unit (SAU) (b) Serial communication operation setting register mn (SCRmn) Table 21.22 Example of serial communication operation setting register mn (SCRmn) contents for master reception of simplified SPI Symbol Set value Function DLS[1:0] Setting of data length...
Page 375 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.25 Example of serial output enable register m (SOEm) contents for master reception of simplified Symbol Set value Function SOE[n] Bit that cannot be used in this mode (set to the initial value when not used in any mode) (f) Serial channel start register m (SSm) Set only the bit of the target channel to 1.
Page 376 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.28 Procedure for stopping master reception Step Process Detail Procedure for <1> Starting setting to stop — stopping master <2> Wait until SSRmn.TSF is cleared (optional) If there is any data being transferred, wait for their completion.
Page 377 RA0E1 User's Manual 21. Serial Array Unit (SAU) SSm.SS[n] STm.ST[n] SEm.SE[n] Receive data 2 Receive data 3 Receive data 1 SDRmn.DAT[7:0] Dummy data for reception Dummy data Dummy data Write Write Write Read Read Read SCKp pin Receive data 2...
Page 378 RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting simplified SPI communication For the initial setting , see SAU initial setting (Select transfer end interrupt) Setting storage area of the receive data, number of communication data Setting receive data (Storage area, Reception data pointer, and number of communication data are...
Page 379 RA0E1 User's Manual 21. Serial Array Unit (SAU) <1> SSm.SS[n] <8> STm.ST[n] SEm.SE[n] Receive data 3 Dummy data Dummy data Receive data 1 Dummy data Receive data 2 SDRmn.DAT[7:0] <2> <2> Write Write <2> Write Read Read Read SCKp pin...
Page 380 RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting simplified SPI communication For the initial setting, see SAU initial setting (Select buffer empty interrupt) <1> Setting storage area of the receive data, number of communication data (Storage area, Reception data pointer, and number of...
Page 381: Master Transmission And Reception
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.5.3 Master Transmission and Reception Master transmission and reception is when a microcontroller outputs a transfer clock and transmits and receives data to and from other device. Table 21.30 shows the specification for master transmission and reception of Simplified SPI.
Page 382 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.31 Example of serial mode register mn (SMRmn) contents for master transmission and reception of simplified SPI (2 of 2) Symbol Set value Function Operation clock (f ) of channel n...
Page 383 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.34 Example of serial output register m (SOm) contents for master transmission and reception of simplified SPI (2 of 2) Symbol Set value Function CKO[n] Communication starts when a bit is 1 if the clock phase is non-reversed (SCRmn.DCP[0] = 0).
Page 384 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.38 Procedure for stopping master transmission and reception Step Process Detail Procedure for <1> Starting setting to stop — stopping master <2> Wait until SSRmn.TSF is cleared (optional) If there is any data being transferred, wait for their completion.
Page 385 RA0E1 User's Manual 21. Serial Array Unit (SAU) SSm.SS[n] STm.ST[n] SEm.SE[n] Receive data 3 Receive data 2 Receive data 1 SDRmn.DAT[7:0] Transmit data 1 Transmit data 2 Transmit data 3 Write Write Write Read Read Read SCKp pin Receive data 1...
Page 386 RA0E1 User's Manual 21. Serial Array Unit (SAU) Start simplified SPI communication For the initial setting, see SAU initial setting (select transfer end interrupt ) Setting storage data and number of data for transmission/reception data Set transmission and (storage area, transmission data pointer, reception data pointer, and...
Page 387 RA0E1 User's Manual 21. Serial Array Unit (SAU) <1> SSm.SS[n] <8> STm.ST[n] SEm.SE[n] Receive data 3 SDRmn.DAT[7:0] Receive data 2 Transmit data 2 Transmit data 1 Receive data 1 Transmit data 3 Write Write Write Read Read Read SCKp pin...
Page 388: Slave Transmission
RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting setting For the initial setting, see SAU initial setting (Select buffer empty interrupt) <1> Setting storage data and number of data for transmission/reception data (Storage area, Transmission data pointer, Reception data, Number of...
Page 389 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.40 Specification of slave transmission of simplified SPI Simplified SPI SPI00 SPI11 SPI20 Target channel Channel 0 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1 Pins used SCK00, SO00...
Page 390 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.41 Example of serial mode register mn (SMRmn) contents for slave transmission of simplified SPI (2 of 2) Symbol Set value Function Operation clock (f ) of channel n 0: Prescaler output clock CKm0 set by the SPSm register...
Page 391 RA0E1 User's Manual 21. Serial Array Unit (SAU) (e) Serial output enable register m (SOEm) Set only the bit of the target channel to 1. Table 21.45 Example of serial output enable register m (SOEm) contents for slave transmission of simplified...
Page 392 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.48 Procedure for stopping slave transmission Step Process Detail Procedure for <1> Starting setting to stop — stopping slave <2> Wait until the SSRmn.TSF bit is cleared If there is any data being transferred, wait for their completion.
Page 393 RA0E1 User's Manual 21. Serial Array Unit (SAU) SSm.SS[n] STm.ST[n] SEm.SE[n] SDRmn.DAT[7:0] Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin Transmit data 1 Transmit data 2 Transmit data 3 SOp pin Shift register mn Shift operation Shift operation...
Page 394 RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting simplified SPI communication For the initial setting, see SAU initial setting (select transfer end interrupt ) Set storage area and the number of data for transmit data (storage area, transmission data pointer, and number of...
Page 395 RA0E1 User's Manual 21. Serial Array Unit (SAU) <1> SSm.SS[n] STm.ST[n] <6> SEm.SE[n] SDRmn.DAT[7:0] Transmit data 2 Transmit data 3 Transmit data 1 SCKp pin Transmit data 1 Transmit data 2 Transmit data 3 SOp pin Shift operation Shift register mn...
Page 396: Slave Reception
RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting setting For the initial setting, see SAU initial setting (Select buffer empty interrupt) <1> Set storage area and the number of data for transmit data Setting transmit data (Storage area, Transmission data pointer, Number of communication data and...
Page 397 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.50 Specification of slave reception of simplified SPI (2 of 2) Simplified SPI SPI00 SPI11 SPI20 Pins used SCK00, SI00 SCK11, SI11 SCK20, SI20 Interrupt SAU0_SPI_TXRXI00 SAU0_SPI_TXRXI11 SAU1_SPI_TXRXI20 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) Error detection flag Overrun error detection flag (SSRmn.OVF) only...
Page 398 RA0E1 User's Manual 21. Serial Array Unit (SAU) (b) Serial communication operation setting register mn (SCRmn) Table 21.52 Example of serial communication operation setting register mn (SCRmn) contents for slave reception of simplified SPI Symbol Set value Function DLS [1:0]...
Page 399 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.56 Example of serial channel start register m (SSm) contents for slave reception of simplified Symbol Set value Function SS[n] Operation start trigger of channel n 1: Set the SEm.SE[n] bit to 1 to place the channel in communication waiting state...
Page 400 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.59 Procedure for resuming slave transmission Step Process Detail Procedure for <1> Start setting for resumption — resuming slave <2> Wait until completing master preparations Wait until the communication target (master) stops or reception communication operation completed.
Page 401: Slave Transmission And Reception
RA0E1 User's Manual 21. Serial Array Unit (SAU) Start simplified SPI communication For the initial setting, see SAU initial setting (select transfer end interrupt) Clear storage area setting and the number of receive data Preparation for reception (storage area, reception data pointer, and number of communication...
Page 402 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.60 Specification of slave transmission and reception of simplified SPI (2 of 2) Simplified SPI SPI00 SPI11 SPI20 Interrupt SAU0_SPI_TXRXI00 SAU0_SPI_TXRXI11 SAU1_SPI_TXRXI20 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
Page 403 RA0E1 User's Manual 21. Serial Array Unit (SAU) (b) Serial communication operation setting register mn (SCRmn) Table 21.62 Example of serial communication operation setting register mn (SCRmn) contents for slave transmission and reception of simplified SPI Symbol Set value Function...
Page 404 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.65 Example of serial output enable register m (SOEm) contents for slave transmission and reception of simplified SPI Symbol Set value Function SOE[n] Serial output enable or stop of channel n 1: Enable output by serial communication operation.
Page 405 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.68 Procedure for stopping slave transmission and reception Step Process Detail Procedure for <1> Starting setting to stop — stopping slave <2> Wait until SSRmn.TSF is cleared (optional) If there is any data being transferred, wait for their completion.
Page 406 RA0E1 User's Manual 21. Serial Array Unit (SAU) SSm.SS[n] STm.ST[n] SEm.SE[n] Receive data 1 Receive data 2 Receive data 3 SDRmn.DAT[7:0] Transmit data 1 Transmit data 2 Transmit data 3 Write Write Write Read Read Read SCKp pin Receive data 2...
Page 407 RA0E1 User's Manual 21. Serial Array Unit (SAU) Start simplified SPI communication For the initial setting, see SAU initial setting (select buffer empty interrupt ) Setting storage area and number of data for transmission and reception Set transmission and data (storage area, transmission and reception data pointer, number of...
Page 408 RA0E1 User's Manual 21. Serial Array Unit (SAU) <1> SSm.SS[n] <8> STm.ST[n] SEm.SE[n] Receive data 3 SDRmn.DAT[7:0] Transmit data 1 Transmit data 2 Receive data 1 Transmit data 3 Receive data 2 Write Write Write Read Read Read SCKp pin...
Page 409 RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting setting For the initial setting, see <1> SAU initial setting (Select buffer empty interrupt) Setting storage area and number of data for transmission and reception data (Storage area, Transmission and reception data pointer, and...
Page 410: Snooze Mode Function
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.5.7 Snooze Mode Function The Snooze mode makes the simplified SPI perform reception operations on SCK00 pin input detection while in the Software Standby mode. Normally the simplified SPI stops communication in the Software Standby mode. However, using the Snooze mode enables the simplified SPI to perform reception operations without CPU operation on detection of the SCK00 pin input.
Page 411 RA0E1 User's Manual 21. Serial Array Unit (SAU) Snooze operation SSR00.TSF = 0 for all channels? <1> Set ST0.ST[0] bit to 1 Stop operation by setting SE0.SE[0] = 0 SMR00, SCR00: Communication setting SAU initial setting SDR00.STCLK[6:0]: Setting 0000000b Setting SSC0 register <2>...
Page 412 RA0E1 User's Manual 21. Serial Array Unit (SAU) Software Software State of the CPU Standby Normal operation Standby Snooze mode Normal operation Snooze mode mode mode <4> <4> <3> <3> SS0.SS[0] <1> <9> ST0.ST[0] SE0.SE[0] SSC0.SWC <10> SSC0.SSEC Clock request signal...
Page 413: Calculating Transfer Clock Frequency
RA0E1 User's Manual 21. Serial Array Unit (SAU) Snooze operation SSR00.TSF = 0 for all channels? <1> Set ST0.ST[0] bit to 1 Stop operation by setting SE0.SE[0] = 0. SMR00, SCR00: Communication setting SAU initial setting SDR00[15:9]: Setting 0x00 Setting SSC0 register <2>...
Page 414 RA0E1 User's Manual 21. Serial Array Unit (SAU) The operation clock (f ) is determined by serial clock select register m (SPSm) and CKS bit of serial mode register mn (SMRmn) as shown in Table 21.70. Table 21.70 Selection of operation clock for simplified SPI, UART and simplified I...
Page 415: Procedure For Processing Errors That Occurred During Simplified Spi Communication
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.5.9 Procedure for Processing Errors that Occurred During Simplified SPI Communication The procedure for processing errors that occurred during simplified SPI communication is described in Table 21.71. Table 21.71 Processing procedure in case of overrun error...
Page 416: Uart Transmission
RA0E1 User's Manual 21. Serial Array Unit (SAU) When the medium-speed on-chip oscillator clock (MOCO) or low-speed on-chip oscillator clock (LOCO) is selected for PCLKB, use the medium-speed on-chip oscillator trimming register (MIOTRM) and low-speed on-chip oscillator trimming register (LIOTRM) to correct oscillation frequency accuracy.
Page 417: Register Setting
RA0E1 User's Manual 21. Serial Array Unit (SAU) Note 2. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see section 31, Electrical Characteristics Register setting Table 21.73...
Page 418 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.74 Example of serial communication operation setting register mn (SCRmn) contents for UART transmission (2 of 2) Symbol Set value Function 13:12 DCP[1:0] Since this bit is dedicated to other modes, it is fixed in the UART mode...
Page 419: Operation Procedure
RA0E1 User's Manual 21. Serial Array Unit (SAU) (g) Serial channel start register m (SSm) Set only the bit of the target channel to 1. Table 21.79 Table 15.84 Example of serial channel start register m (SSm) contents for UART...
Page 420 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.82 shows the procedure for resuming UART transmission. Table 21.82 Procedure for resuming UART transmission Step Process Detail Procedure for <1> Starting setting for resumption — resuming UART <2> Wait until Communication target is ready...
Page 421 RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting UART communication For the initial setting, see SAU initial setting (Select transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag (Storage area, transmission data pointer,...
Page 422 RA0E1 User's Manual 21. Serial Array Unit (SAU) <1> SSm.SS[n] <6> STm.ST[n] SEm.SE[n] SDRmn.DAT[8:0] Transmit data 1 Transmit data 2 Transmit data 3 or DAT[7:0] TXDq pin P SP Transmit data 1 Transmit data 2 Transmit data 3 Shift register mn...
Page 423: Uart Reception
RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting UART communication <1> For the initial setting, see SAU initial setting (Select buffer empty interrupt) Set the data pointer for transmission and the number of data items. Clear Setting transmit data...
Page 424 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.83 Specification of UART reception (2 of 2) UART UART0 UART1 UART2 Interrupt SAU0_UART_RXI0 SAU0_UART_RXI1 SAU1_UART_RXI2 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) Error interrupt SAU0_UART_ERRI0 SAU0_UART_ERRI1...
Page 425 RA0E1 User's Manual 21. Serial Array Unit (SAU) (b) Serial mode register mr (SMRmr) Table 21.85 Example of serial mode register mr (SMRmr) contents for UART reception Symbol Set value Function Interrupt source of channel r 0: Transfer end interrupt...
Page 426 RA0E1 User's Manual 21. Serial Array Unit (SAU) (d) Serial data register mn (SDRmn) Table 21.87 Example of serial data register mn (SDRmn) contents for UART reception Symbol Set value Function DAT[6:0] 0x00 Receive data[6:0] 0x7F DAT[7] Receive data[7] (8-bit and 9-bit data length)
Page 427 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.91 Initial setting procedure for UART reception Step Process Detail Procedure for initial <1> Starting initial setting — setting of UART <2> Setting the SPSm register Set the operation clock. reception <3>...
Page 428: Processing Flow
RA0E1 User's Manual 21. Serial Array Unit (SAU) Processing flow Figure 21.35 shows the timing of UART reception. SSm.SS[n] STm.ST[n] SEm.SE[n] Receive data 3 SDRmn.DAT[8:0] or DAT[7:0] Receive data 1 Receive data 2 RXDq pin Receive data 3 Receive data 1...
Page 429: Snooze Mode Function
RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting UART communication For the initial setting, see SAU initial setting (setting to mask for error interrupt) Setting storage area of the receive data, number of communication Setting receive data data (storage area, reception data pointer, number of communication...
Page 430 RA0E1 User's Manual 21. Serial Array Unit (SAU) Note: The Snooze mode can only be used when the high-speed on-chip oscillator clock or medium-speed on-chip oscillator clock is selected for PCLKB. When the medium-speed on-chip oscillator clock is selected, use the Middle-speed On-chip Oscillator Trimming Register (MIOTRM) to correct the accuracy of the oscillation frequency.
Page 431 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.95 Baud rate setting for UART reception in Snooze mode when starting of the high-speed on-chip oscillator is at high speed (FWKUP = 1) Operating clock High-speed on-chip Maximum Minimum Baud rate...
Page 432 RA0E1 User's Manual 21. Serial Array Unit (SAU) Snooze mode operation (SCR01.EOC = 1, SSC0.SSEC = 0: Error interrupt (SAU0_UART_ERRI0) generation is enabled) Because SCR01.EOC = 1 and SSC0.SSEC = 0, an error interrupt (SAU0_UART_ERRI0) is generated when a communication error occurs.
Page 433 RA0E1 User's Manual 21. Serial Array Unit (SAU) Setting start Does SSR01.TSF = 0 on all channels? <1> Writing 1 to the ST0.ST[1] bit The operation of all channels is also stopped to switch to the ® SE0.SE[1] = 0 Software Standby mode.
Page 434 RA0E1 User's Manual 21. Serial Array Unit (SAU) Normal operation Software Standby Software mode State of the CPU Normal operation Standby Snooze mode Snooze mode mode <3> <4> SS0.SS[1] <1> <10> ST0.ST[1] SE0.SE[1] <11> SSC0.SWC <11> SCR01.EOC SSC0.SSEC Clock request signal...
Page 435: Calculating Baud Rate
RA0E1 User's Manual 21. Serial Array Unit (SAU) Setting start Does SSR01.TSF = 0 on all channels? SIR01 = 0x0007 Clear the all error flags The operation of all channels is also stopped to switch to Writing 1 to the ST0.ST[1] bit <1>...
Page 436 RA0E1 User's Manual 21. Serial Array Unit (SAU) The operation clock (f ) is determined by serial clock select register m (SPSm) and CKS bit of serial mode register mn (SMRmn). See Table 21.70. Baud rate error during transmission The baud rate error of UART communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 437: Procedure For Processing Errors That Occurred During Uart Communication
RA0E1 User's Manual 21. Serial Array Unit (SAU) Latch timing Parity Stop Data frame length Start Bit 0 Bit 1 Bit 7 of SAU 1 data frame (11 × FL) Start Stop Parity Permissible minimum Bit 0 Bit 1 Bit 7 data frame length (11 ×...
Page 438: Operation Of Lin Communication
RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.98 Processing procedure for framing error (2 of 2) Step Software manipulation State of the hardware Note <5> Synchronization with other party of — Synchronization with the other party communication of communication is re-established...
Page 439 RA0E1 User's Manual 21. Serial Array Unit (SAU) Protected Sync field Data field Data field Wakeup signal Break field Checksum Identifier frame field field LIN Bus 13-bit length 0x55 Data Data Checksum Break transmission transmission transmission transmission transmission 8-bit length...
Page 440 RA0E1 User's Manual 21. Serial Array Unit (SAU) Starting LIN Operation of the hardware (Reference) communication Transmitting wakeup signal frame (0x80 ® TXD2) Wakeup signal frame generation SSR10.TSF = 0? Transmitting wakeup 8-bit length TXD2 signal frame UART2 stop Waiting for completion 0x80 (1 ®...
Page 441: Lin Reception
RA0E1 User's Manual 21. Serial Array Unit (SAU) 21.7.2 LIN Reception Of UART reception, UART2 supports LIN communication. For LIN reception, channel 1 of unit 1 is used. Table 21.100 shows the specification of LIN reception. Table 21.100 Specification of LIN reception...
Page 442 RA0E1 User's Manual 21. Serial Array Unit (SAU) Protected Wakeup signal Checksum Break field Sync field identifier Data field Data field frame field field LIN Bus Response Header Break 0x55 Data Checksum Data reception reception reception reception reception reception <5>...
Page 443 RA0E1 User's Manual 21. Serial Array Unit (SAU) State of LIN bus signal and operation Starting LIN of the hardware communication Wakeup signal frame Wait for wakeup frame signal Generate IRQ0? RXD2 pin Edge detection The low-level width of RXD2 is...
Page 444: Operation Of Simplified I C Communication
RA0E1 User's Manual 21. Serial Array Unit (SAU) RXD2 RXD2 input Selector IRQ0 IRQ0 input Port input switch control (ISC0) <ISC0> 0: Selects IRQ0 pin 1: Selects RXD2 pin Selector TI07 Channel 7 input of timer array unit Port input...
Page 445: Address Field Transmission
RA0E1 User's Manual 21. Serial Array Unit (SAU) ● Data length of 8 bits (when an address is transmitted, the address is specified by the upper 7 bits, and the least significant bit is used for R/W control.) ● Generation of start condition and stop condition for software [Interrupt function] ●...
Page 446: Register Setting
RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.101 Specification of address field transmission of simplified I C (2 of 2) Simplified I IIC00 IIC11 IIC20 Data level Non-reverse output (default: high level) Parity bit No parity bit Stop bit...
Page 447 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.103 Example of serial communication operation setting register mn (SCRmn) contents for address field transmission of simplified I C (2 of 2) Symbol Set value Function This bit is fixed in simplified I C mode because it is for simplified SPI and UART modes.
Page 448 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.107 Example of serial channel start register m (SSm) contents for address field transmission of simplified I Symbol Set value Function SS[n] Operation start trigger of channel n 0: No trigger operation 1: Set the SEm.SE[n] bit to 1 to place the channel in the communications waiting...
Page 449: Data Transmission
RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.109 Procedure for simplified I C address field transmission Step Process Detail Procedure for <1> Transmitting address field — simplified I <2> Default setting For the initial setting, see Table 21.108.
Page 450 RA0E1 User's Manual 21. Serial Array Unit (SAU) Register setting Table 21.111 Table 21.116 show examples of the register contents for data transmission of simplified I (a) Serial mode register mn (SMRmn) Do not manipulate this register during data transmission and reception.
Page 451 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.113 Example of serial data register mn (SDRmn) contents for data transmission of simplified I Symbol Set value Function DAT[7:0] 0x00 Transmit data (Transmit data setting) 0xFF DAT[8] 0 Fixed 15:9...
Page 452: Data Reception
RA0E1 User's Manual 21. Serial Array Unit (SAU) SSm.SS[n] “L” SEm.SE[n] “H” SOEm.SOE[n] “H” SDRmn.DAT[7:0] Transmit data 1 SCLr output SDAr output SDAr input Shift register mn Shift operation SAUm_IIC_TXRXIr SSRmn.TSF Figure 21.49 Timing of data transmission Table 21.117 shows the procedure for simplified I C data transmission.
Page 453 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.118 Specification of data reception of simplified I C (2 of 2) Simplified I IIC00 IIC11 IIC20 Max.f /4 [Hz] (SDRmn.STCLK[6:0] = 1 or more) Transfer rate However, the following conditions must be satisfied in each mode of I ●...
Page 454 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.120 Example of serial communication operation setting register mn (SCRmn) contents for data reception of simplified I Symbol Set value Function DLS[1:0] Setting of data length 1 1: 8-bit data length —...
Page 455 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.124 Example of serial channel start register m (SSm) contents for data reception of simplified Symbol Set value Function SS[n] Operation start trigger of channel n 0: No trigger operation 1: Set the SEm.SE[n] bit to 1 to place the channel in the communications waiting state.
Page 456 RA0E1 User's Manual 21. Serial Array Unit (SAU) (a) When starting data reception SSm.SS[n] STm.ST[n] SEm.SE[n] SOEm.SOE[n] “H” SCRmn.TRXE[1:0] TRXE[1:0] = 01b TRXE[1:0] = 10b SDRmn.DAT [7:0] Dummy data (0xFF) Receive data SCLr output SDAr output SDAr input Shift register mn...
Page 457: Stop Condition Generation
RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.125 Procedure for data reception Step Process Detail Procedure for data <1> Address field transmission completed — reception <2> Data reception — <3> Writing 1 to the STm.ST[n] bit Stop operation for rewriting SCRmn register.
Page 458: Calculating Transfer Rate
RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.126 Procedure for stop condition generation Step Process Detail Procedure for stop <1> Completion of data transmission and data — condition generation reception <2> Starting generation of stop condition — <3>...
Page 459 RA0E1 User's Manual 21. Serial Array Unit (SAU) Table 21.128 Processing procedure for overrun error Step Software manipulation State of the hardware Remark <1> Read serial data register mn The BFF bit of the SSRmn register is This is to prevent an overrun error (SDRmn).
Page 460: C Bus Interface (Iica)
RA0E1 User's Manual 22. I2C Bus Interface (IICA) C Bus Interface (IICA) 22.1 Overview The I C bus interface has the following three modes: ● Operation stop mode ● I C bus mode (multimaster supported) ● Wakeup mode Table 22.1 shows specifications of the I C bus interface.
Page 461 RA0E1 User's Manual 22. I2C Bus Interface (IICA) Table 22.1 C specifications (2 of 2) Parameter Specifications Wakeup function CPU can return from Software Standby mode and Snooze mode using a wakeup event Figure 22.1 shows a block diagram of the I C bus interface.
Page 462 RA0E1 User's Manual 22. I2C Bus Interface (IICA) Wakeup mode The Software Standby mode can be released by generating an interrupt request signal (IICA0_TXRXI) when an extension code from the master device or the local address has been received while in Software Standby mode. This can be set by using the WUP bit of IICA control register 01 (IICCTL01).
Page 463: Register Descriptions
RA0E1 User's Manual 22. I2C Bus Interface (IICA) Power supply for pull-up SCLAn SCLin SCLout# SDAAn SDAin SDAout# (Master) SCLin SCLin SCLout# SCLout# SDAin SDAin SDAout# SDAout# (Slave 1) (Slave 2) Note: n = 0 Figure 22.2 Example of the serial bus configuration using the I C bus 22.2...
Page 464: Sva0 : Slave Address Register 0
RA0E1 User's Manual 22. I2C Bus Interface (IICA) When communication is reserved, write data to the IICA0 register after the interrupt triggered by a stop condition is detected. 22.2.2 SVA0 : Slave Address Register 0 Base address: IICA = 0x400A_3000...
Page 465 RA0E1 User's Manual 22. I2C Bus Interface (IICA) Symbol Function Control of Clock Stretching and Interrupt Request Generation WTIM 0: An interrupt request is generated on the falling edge of the 8th clock cycle. Master mode: After the output of eight clock pulses, the clock output is set to the low level and clock stretching is set.
Page 466 RA0E1 User's Manual 22. I2C Bus Interface (IICA) SPT bit (Stop Condition Trigger) Cautions concerning set timing ● For master reception: Cannot be set to 1 during transfer. After setting the ACKE bit to 0, telling the slave device that it is the last to receive, this bit can be set to 1 only during the clock stretch period.
Page 467 RA0E1 User's Manual 22. I2C Bus Interface (IICA) ● Set by instruction ACKE bit (Acknowledgment Control) Condition for clearing (ACKE = 0) ● Cleared by instruction ● Reset Condition for setting (ACKE = 1) ● Set by instruction WTIM bit (Control of Clock Stretching and Interrupt Request Generation) An interrupt is generated on the falling edge of the ninth clock cycle during address transfer independently of the setting of this bit.
Page 468: Iics0 : Iica Status Register 0
RA0E1 User's Manual 22. I2C Bus Interface (IICA) Condition for clearing (LREL = 0) ● Automatically cleared after execution ● Reset Condition for setting (LREL = 1) ● Set by instruction IICE bit (I C Operation Enable) Be sure to set this bit to 1 while the SCLA0 and SDAA0 lines are at high level.
Page 469 RA0E1 User's Manual 22. I2C Bus Interface (IICA) Symbol Function MSTS Master Status Check Flag 0: Slave mode status or communication standby status 1: Master mode communication status This register indicates the state of the I The IICS0 register can only be read while the setting of IICCTL00.STT is 1 or this module is in the clock stretch state.
Page 470 RA0E1 User's Manual 22. I2C Bus Interface (IICA) ● Cleared by IICCTL00.LREL = 1 (exit from communications) ● When the IICCTL00.IICE bit changes from 1 to 0 (operation stop) ● Cleared by IICCTL00.WREL = 1 (release from the clock stretch state) ●...
Page 471: Iicf0 : Iica Flag Register 0
RA0E1 User's Manual 22. I2C Bus Interface (IICA) ● Reset Condition for setting (EXC = 1) ● When the higher four bits of the received address data is either 0000b or 1111b (set at the rising edge of the eighth clock).
Page 472 RA0E1 User's Manual 22. I2C Bus Interface (IICA) Symbol Function STCF IICCTL00.STT Clear Flag 0: Generate start condition 1: Start condition generation unsuccessful: clear the IICCTL00.STT flag This register sets the operation mode of I C and indicates the state of the I C bus.
Page 473: Iicctl01 : Iica Control Register 01
RA0E1 User's Manual 22. I2C Bus Interface (IICA) ● Reset Condition for setting (STCF = 1) ● Generating start condition unsuccessful and the IICCTL00.STT bit cleared to 0 when communication reservation is disabled (IICRSV = 1). 22.2.6 IICCTL01 : IICA Control Register 01...
Page 474 RA0E1 User's Manual 22. I2C Bus Interface (IICA) PRS bit (IICA Operation Clock (f The PRS bit is used to set IICA operation clock (f DFC bit (Digital Filter Operation Control) Use the digital filter only in fast mode and fast mode plus.
Page 475: Iicwl0 : Iica Low-Level Width Setting Register 0
RA0E1 User's Manual 22. I2C Bus Interface (IICA) ● Set by instruction (when the IICS0.MSTS, IICS0.EXC, and IICS0.COI bits are 0, and the IICS0.STD bit also 0 (communication not entered)) The status of the IICA status register 0 (IICS0) must be checked and the WUP bit must be set during the period shown in Figure 22.3.
Page 476: Registers To Control The Port Function Multiplexed With The I 2 C I/O Pins
RA0E1 User's Manual 22. I2C Bus Interface (IICA) Set the IICWH0 register while the I C operation is disabled (IICCTL00.IICE). For the procedures for setting the transfer clock in master mode and the IICWL0 and IICWH0 registers in slave mode, refer...
Page 477: Start Conditions
RA0E1 User's Manual 22. I2C Bus Interface (IICA) IICWH0 = − t − t × f 0.48 Transfer clock IICWL0 = × f 0.47 ● When the normal mode Transfer clock IICWH0 = − t − t × f 0.53...
Page 478: Address
RA0E1 User's Manual 22. I2C Bus Interface (IICA) 22.3.4 Address The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 479: Stop Condition
RA0E1 User's Manual 22. I2C Bus Interface (IICA) When the master device receives the last data item, it does not return ACK and instead generates a stop condition. If a slave device does not return ACK after receiving data, the master device outputs a stop condition or restart condition and stops transmission.
Page 480: Clock Stretching
RA0E1 User's Manual 22. I2C Bus Interface (IICA) SCLAn SDAAn Note: n = 0 Figure 22.9 Stop condition A stop condition is generated when SPT bit of IICA control register 00 (IICCTL00) is set to 1. When the stop condition is detected, SPD bit of the IICA status register 0 (IICS0) is set to 1 and IICA0_TXRXI is generated when SPIE bit of the IICCTL00 register is set to 1.
Page 481: Release From Clock Stretching
RA0E1 User's Manual 22. I2C Bus Interface (IICA) When clock stretching is set for the 9th clock cycle for both the master and slave devices (master: transmission, slave: reception, and IICCTL00.ACKE = 1) The clock is stretched after the output...
Page 482: Timing Of Generation Of The Interrupt Request Signal (Iica0_Txrxi) And Control Of Clock Stretching
RA0E1 User's Manual 22. I2C Bus Interface (IICA) Execute the processing for release only once for each period in the clock stretch state. If, for example, data is written to the IICA0 register after release from the clock stretch state by setting the IICCTL00.WREL bit to 1, an incorrect value may be output to SDAA0 line because the timing for changing the SDAA0...
Page 483: Address Match Detection Method
RA0E1 User's Manual 22. I2C Bus Interface (IICA) At this point, ACK is generated regardless of the value set to the IICCTL00.ACKE bit. For a slave device that has received an extension code, or has received an address while the all address match function is enabled, IICA0_TXRXI occurs at the falling edge of the eighth clock.
Page 484: Arbitration
RA0E1 User's Manual 22. I2C Bus Interface (IICA) 22.3.14 Arbitration When several master devices simultaneously generate a start condition (when the IICCTL00.STT bit is set to 1 before the IICS0.STD bit is set to 1), communication among the master devices is performed as the clocks are adjusted until the data differs.
Page 485: Wakeup Function
RA0E1 User's Manual 22. I2C Bus Interface (IICA) Note 1. When the IICCTL00.WTIM = 1, an interrupt request occurs at the falling edge of the ninth clock. When IICCTL00.WTIM = 0, the extension code's slave address is received, and an address is received while the all address match function is enabled, an interrupt request occurs at the falling edge of the 8th clock.
Page 486: Communication Reservation
RA0E1 User's Manual 22. I2C Bus Interface (IICA) When released by other than IICA0_TXRXI interrupt: Wait for IICA0_TXRXI interrupt with IICCTL01.WUP left set to 1. Table 22.7 When operating as master device after releasing Software Standby mode other than by...
Page 487 RA0E1 User's Manual 22. I2C Bus Interface (IICA) : SDAA0 and SCLA0 signal falling times : IICA operation clock frequency Figure 22.13 shows the communication reservation timing. Write to IICCTLn0 Program processing .STT = 1 IICAn Communi- Set IICSn.SPD Hardware processing cation IICSn.STD...
Page 488: Usage Notes
RA0E1 User's Manual 22. I2C Bus Interface (IICA) Disable interrupts Sets IICCTLn0.STT flag (communication Set IICCTLn0.STT reservation) Defines that communication reservation is in effect Define communication (defines and sets user flag to any part of RAM) reservation Secures wait time by software.
Page 489: Communication Operations
RA0E1 User's Manual 22. I2C Bus Interface (IICA) 2. When IICF0.STCEN = 1 Immediately after I C operation is enabled (IICCTL00.IICE = 1), the bus released status (IICF0.IICBSY = 0) is recognized regardless of the actual bus status. To generate the first start condition (IICCTL00.STT = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications.
Page 490 RA0E1 User's Manual 22. I2C Bus Interface (IICA) START Setting the MSTPCRB register Cancel the module-stop state and start clock supply. Initializing I C bus Setting of the port multiplexed with the pin to be used. Setting port First, set the port to input mode IICWLn, IICWHn ¬...
Page 491 RA0E1 User's Manual 22. I2C Bus Interface (IICA) START Cancel the Module-stop state and start clock supply. Setting the MSTPCRB register Setting of the port multiplexed with the pin to be used. Setting port First, set the port to input mode IICWLn, IICWHn ¬...
Page 492 RA0E1 User's Manual 22. I2C Bus Interface (IICA) Enable reserving communication. Prepare for starting communication IICCTLn0.STT = 1 (generate a start condition). Secure wait time Wait by software. IICSn.MSTS = 1? IICAn_TXRXI interrupt occurs? Wait for bus release (communication being reserved).
Page 493 RA0E1 User's Manual 22. I2C Bus Interface (IICA) Start communication Writing IICAn (specify an address and transfer direction). IICAn_TXRXI interrupt occurs? Wait for detection of ACK. IICSn.MSTS = 1? IICSn.ACKD = 1? IICCTLn0.ACKE = 1 IICCTLn0.WTIM = 0 IICSn.TRC = 1? IICCTLn0.WREL = 1...
Page 494 RA0E1 User's Manual 22. I2C Bus Interface (IICA) IICAn_TXRXI Flag Interrupt servicing Setting IICA Main processing Data Setting Note: n = 0 Figure 22.20 Interface configuration with the main processor in slave device operation Therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of IICA0_TXRXI.
Page 495 RA0E1 User's Manual 22. I2C Bus Interface (IICA) START Setting the MSTPCRB register Cancel the module-stop state and start clock supply. Setting of the port multiplexed with the pin to be used. Setting port First, set the port to input mode IICWLn, IICWHn ¬...
Page 496: Timing Of I C Interrupt Request Signal (Iica0_Txrxi) Occurrence
RA0E1 User's Manual 22. I2C Bus Interface (IICA) If the address matches, the communication mode is set, wait is canceled, and processing returns from the interrupt (the ready flag is cleared). <3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I C bus remaining in the communication standby status.
Page 497: Master Device Operation
RA0E1 User's Manual 22. I2C Bus Interface (IICA) Master device operation (a) Start → Address → Data → Data → Stop (reception/transmission) 1. When IICCTL00.WTIM = 0 IICCTLn0.SPT = 1 ¯ AD6 to AD0 R/W# ACK D7 to D0 D7 to D0 ▲1: IICSn = 1000x110b...
Page 498 RA0E1 User's Manual 22. I2C Bus Interface (IICA) (b) Start → Address → Data → Start → Address → Data → Stop (restart) 1. When IICCTL00.WTIM = 0 IICCTLn0.STT = 1 IICCTLn0.SPT = 1 ¯ ¯ AD6 to AD0 R/W# ACK...
Page 499 RA0E1 User's Manual 22. I2C Bus Interface (IICA) (c) Start → Code → Data → Data → Stop (extension code transmission) 1. When IICCTL00.WTIM = 0 IICCTLn0.SPT = 1 ¯ AD6 to AD0 R/W# ACK D7 to D0 D7 to D0 ▲1: IICSn = 1010x110b...
Page 500 RA0E1 User's Manual 22. I2C Bus Interface (IICA) 2. When IICCTL00.WTIM = 1 AD6 to AD0 R/W# ACK D7 to D0 D7 to D0 ▲1: IICSn = 0001x110b ▲2: IICSn = 0001x100b ▲3: IICSn = 0001xx00b △4: IICSn = 00000001b...
Page 501 RA0E1 User's Manual 22. I2C Bus Interface (IICA) AD6 to AD0 R/W# ACK D7 to D0 AD6 to AD0 R/W# D7 to D0 ▲1: IICSn = 0001x110b ▲2: IICSn = 0001x000b ▲3: IICSn = 0010x010b ▲4: IICSn = 0010x000b △5: IICSn = 00000001b...
Page 502 RA0E1 User's Manual 22. I2C Bus Interface (IICA) AD6 to AD0 R/W# ACK D7 to D0 AD6 to AD0 R/W# D7 to D0 ▲1: IICSn = 0001x110b ▲2: IICSn = 0001xx00b ▲3: IICSn = 00000x10b △4: IICSn = 00000001b Note:...
Page 503 RA0E1 User's Manual 22. I2C Bus Interface (IICA) (b) Start → Code → Data → Start → Address → Data → Stop 1. When IICCTL00.WTIM = 0 (after restart, matches with SVA0, the all address match function is disabled) AD6 to AD0 R/W# ACK...
Page 504 RA0E1 User's Manual 22. I2C Bus Interface (IICA) 2. When IICCTL00.WTIM = 1 (after restart, extension code reception, the all address match function is disabled) AD6 to AD0 R/W# ACK D7 to D0 AD6 to AD0 R/W# D7 to D0 ▲1: IICSn = 0010x010b...
Page 505: Operation Without Communication
RA0E1 User's Manual 22. I2C Bus Interface (IICA) Operation without communication (a) Start → Code → Data → Data → Stop AD6 to AD0 R/W# ACK D7 to D0 D7 to D0 △1: IICSn = 00000001b Note: n = 0 △: Generated only when IICCTLn0.SPIE = 1...
Page 506: Operation When Arbitration Loss Occurs (No Communication After Arbitration Loss)
RA0E1 User's Manual 22. I2C Bus Interface (IICA) (b) When arbitration loss occurs during transmission of extension code (the all address match function is disabled) 1. When IICCTL00.WTIM = 0 AD6 to AD0 R/W# ACK D7 to D0 D7 to D0 ▲1: IICSn = 0110x010b...
Page 507 RA0E1 User's Manual 22. I2C Bus Interface (IICA) (b) When arbitration loss occurs during transmission of extension code (the all address match function is disabled) AD6 to AD0 R/W# ACK D7 to D0 D7 to D0 ▲1: IICSn = 0110x010b Sets IICCTLn0.LREL = 1 by software...
Page 508 RA0E1 User's Manual 22. I2C Bus Interface (IICA) (d) When loss occurs due to restart condition during data transfer 1. Not extension code (Example: unmatches with SVA0, the all address match function is disabled) AD6 to AD0 R/W# ACK D7 to Dm...
Page 509 RA0E1 User's Manual 22. I2C Bus Interface (IICA) (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition 1. When IICCTL00.WTIM = 0 IICCTLn0.STT = 1 ¯ AD6 to AD0 R/W# ACK D7 to D0...
Page 510 RA0E1 User's Manual 22. I2C Bus Interface (IICA) (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition 1. When IICCTL00.WTIM = 0 IICCTLn0.STT = 1 ¯ AD6 to AD0 R/W# ACK D7 to D0 ▲1: IICSn = 1000x110b...
Page 511: Timing Charts
RA0E1 User's Manual 22. I2C Bus Interface (IICA) 1. When IICCTL00.WTIM = 0 IICCTLn0.SPT = 1 ¯ AD6 to AD0 R/W# ACK D7 to D0 D7 to D0 D7 to D0 ▲1: IICSn = 1000x110b ▲2: IICSn = 1000x000b (Set the IICCTLn0.WTIM bit to 1) ▲3: IICSn = 1000x100b (Clear the IICCTLn0.WTIM bit to 0)
Page 512 RA0E1 User's Manual 22. I2C Bus Interface (IICA) Example of Master device to Slave device Communications (When the master device and the slave device insert clock stretching on the 9th cycle.) 1. Start condition → address → data Master side...
Page 513 RA0E1 User's Manual 22. I2C Bus Interface (IICA) <2> The master device writes the address + W (transmission) to the IICA shift register 0 (IICA0) and transmits the slave address. <3> In the slave device if the address received matches the address (SVA0 value) of a slave device, that slave device sends an ACK by hardware to the master device.
Page 514 RA0E1 User's Manual 22. I2C Bus Interface (IICA) 2. Address → data → data Master side Data shift IICAn Data shift +Output (D [7:0]) <5> <9> IICSn.ACKD (ACK detection) IICCTLn0.WTIM (8th or 9th cycle clock stretching) IICCTLn0.ACKE (ACK control) IICSn.MSTS (communication status) IICCTLn0.STT...
Page 515 RA0E1 User's Manual 22. I2C Bus Interface (IICA) <6> If the slave device releases the clock stretch state (IICCTL00.WREL = 1), the master device starts transferring data to the slave device. <7> After data transfer is completed, because of IICCTL00.ACKE = 1, the slave device sends an ACK by hardware to the master device.
Page 516 RA0E1 User's Manual 22. I2C Bus Interface (IICA) 3. Data → data → stop condition Master side Data shift +Output (D [7:0]) IICAn <9> IICSn.ACKD (ACK detection) IICCTLn0.WTIM (8th or 9th cycle clock stretching) IICCTLn0.ACKE (ACK control) IICSn.MSTS (communication status) IICCTLn0.STT...
Page 517 RA0E1 User's Manual 22. I2C Bus Interface (IICA) <10>The slave device reads the received data and releases the clock stretch state (IICCTL00.WREL = 1). The master device then starts transferring data to the slave device. <11>When data transfer is complete, the slave device (IICCTL00.ACKE = 1) sends an ACK by hardware to the master device.
Page 518 RA0E1 User's Manual 22. I2C Bus Interface (IICA) 4. Data → restart condition → address Master side IICAn Output (D [7:0]) Data shift +Output (AD[6:0] + R/W#) <iii> IICSn.ACKD (ACK detection) IICCTLn0.WTIM (8th or 9th cycle clock stretching) IICCTLn0.ACKE (ACK control) IICSn.MSTS...
Page 519 RA0E1 User's Manual 22. I2C Bus Interface (IICA) <ii> The start condition trigger is set again by the master device (IICCTL00.STT = 1) and a start condition (SCLA0 = 1 and SDAA0 changes from 1 to 0) is generated once the bus clock line goes high (SCLA0 = 1) and the bus data line goes low (SDAA0 = 0) after the restart condition setup time has elapsed.
Page 520 RA0E1 User's Manual 22. I2C Bus Interface (IICA) Example of Slave device to Master device Communications (8th Cycle Clock Stretching Is Selected for the Master device and 9th Cycle Clock Stretching Is Selected for the Slave device) 1. Start condition → address → data...
Page 521 RA0E1 User's Manual 22. I2C Bus Interface (IICA) <2> The master device writes the address + R (reception) to the IICA shift register 0 (IICA0) and transmits the slave address. <3> In the slave device if the address received matches the address (SVA0 value) of a slave device, that slave device sends an ACK by hardware to the master device.
Page 522 RA0E1 User's Manual 22. I2C Bus Interface (IICA) 2. Address → data → data Master side Input IICAn Input + Data shift (D [7:0]) IICSn.ACKD (ACK detection) IICCTLn0.WTIM <5> (8th or 9th cycle clock stretching) IICCTLn0.ACKE (ACK control) IICSn.MSTS (communication status) IICCTLn0.STT...
Page 523 RA0E1 User's Manual 22. I2C Bus Interface (IICA) <6> The slave device writes the data to transmit to the IICA shift register 0 (IICA0) and releases the clock stretch state set by the slave device. <7> The master device releases the clock stretch state (IICCTL00.WREL = 1) and starts transferring data from the slave device to the master device.
Page 524 RA0E1 User's Manual 22. I2C Bus Interface (IICA) 3. Data → data → stop condition Master side IICAn Input + Data shift (D [7:0]) IICSn.ACKD (ACK detection) IICCTLn0.WTIM (8th or 9th cycle clock stretching) <14> IICCTLn0.ACKE (ACK control) IICSn.MSTS (communication status) IICCTLn0.STT...
Page 525 RA0E1 User's Manual 22. I2C Bus Interface (IICA) <12>By the slave device writing the data to transmit to the IICA0 register, the clock stretch state set by the slave device is released. The slave device then starts transferring data to the master device.
Page 526: Serial Interface Uarta (Uarta)
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Serial Interface UARTA (UARTA) 23.1 Overview The serial interface UARTA has one channel. Table 23.1 lists specifications of the serial interface UARTA. Table 23.1 UARTA specifications Item Specifications Serial interface modes ● Operation stop mode ●...
Page 527 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) UARTAn RXDAn RXDAn Reception unit ASIMAn1.ALV Inversion control UARTAn_RXI Filter UARTAn_ERRI Reception control Receive shift register Baud rate generator RXBAn Internal bus UTAnCK.CK[3:0] Clock ASIMAn0 ASISAn control FSXP Register UTA0CK.SEL[1:0] block BRGCAn...
Page 528: Register Descriptions
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) 23.2 Register Descriptions 23.2.1 TXBA0 : Transmit Buffer Register 0 Base address: UARTA = 0x400A_3400 Offset address: 0x0000 Bit position: Bit field: Value after reset: Symbol Function Transmit Data Buffer TXBA0 is a buffer register for setting transmit data.
Page 529: Asima00 : Operation Mode Setting Register 00
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) The receive shift register cannot be manipulated directly by software. When a character length of 8 bits is specified: ● Receive data is transferred to bits [7:0] of this register. When a character length of 7 bits is specified: ●...
Page 530: Asima01 : Operation Mode Setting Register 01
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) ● When ASIMA01.ALV = 1, the setting must be made while the level being input to the RXDA0 pin is low. Otherwise, reception starts at that point and a framing error may occur.
Page 531: Brgca0 : Baud Rate Generator Control Register 0
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) 23.2.5 BRGCA0 : Baud Rate Generator Control Register 0 Base address: UARTA = 0x400A_3400 Offset address: 0x0004 Bit position: Bit field: Value after reset: Symbol Function Controls the UART Baud Rate (Serial Transfer Speed)
Page 532 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Symbol Function TXBFA Transmit Buffer Data Flag 0: No valid data exists in the TXBA0 register 1: Valid data exists in the TXBA0 register — These bits are read as 0. The ASISA0 register indicates the error status and the transmission status on completion of reception by the serial interface UARTA0.
Page 533: Ascta0 : Status Clear Trigger Register 0
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) ● The ASIMA00.EN or TXEA bit is cleared to 0. ● Data is transferred from the transmit shift register and then no subsequent data is transferred from the TXBA0 register. [Setting condition] ●...
Page 534: Uta0Ck : Uarta Clock Select Register 0
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) 23.2.8 UTA0CK : UARTA Clock Select Register 0 Base address: UARTA = 0x400A_3400 Offset address: 0x0100 Bit position: Bit field: — — SEL[1:0] CK[3:0] Value after reset: Symbol Function CK[3:0] UARTA0 Operation Clock Select (f...
Page 535: Operation
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Symbol Function ULBS2 Selection of the UART2 Loopback Function 0: Inputs the states of the RXD2 pin of serial array unit UART2 to the reception shift register. 1: Loops back output from the transmission shift register to the reception shift register.
Page 536 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Table 23.3 Step of communication procedure Step Process Detail Step of communication <1> Enable clock supply Set bit 15 of the MSTPCRB register to 0. procedure <2> Baud rate setting Set the BRGCA0 register.
Page 537 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Character length: 8 bits, LSB first, Even parity, Stop bit: 1 bit, Transfer data: 0x55 One data frame Start Parity Stop Character length: 8 bits, MSB first, Even parity, Stop bit: 1 bit, Transfer data: 0x55...
Page 538 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) ● In reception In the data for reception, including the parity bit, the number of bits with the value 1, is counted. If it is even, a parity error occurs. (c) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.
Page 539: Continuous Transmission
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) (1) When ASIMAn0.ISSMA = 0 (transfer completion interrupt) Stop bit: 1 bit One data frame Start Parity Stop UARTAn_TXI Stop bit: 2 bits One data frame Start Parity Stop Stop UARTAn_TXI (2) When ASIMAn0.ISSMA = 1 (buffer empty interrupt)
Page 540 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Continuous transmission is achieved by polling the transmit buffer data flag (bit 5: TXBFA) and the transmit shift register data flag (bit 4: TXSFA) of the status register (ASISA0). When using this method, clear bit 1 (ISSMA) of the operation mode setting register 00 (ASIMA00) to 0.
Page 541 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Continuous transmission is achieved by using the interrupt (UARTA0_TXI). An interrupt can be generated when data in the transmit buffer register (TXBA0) are transferred to the transmit shift register by setting bit 1 (ISSMA) to 1 in the operation mode setting register 00 (ASIMA00).
Page 542 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) TXDAn Data n - 1 Data n Parity Stop Start Parity Start Parity Stop Stop ASIMAn0.ISSMA Output when ASIMAn0.ISSMA = 0 UARTAn_TXI TXBAn Data n - 1 Data n Shift register Data n - 1...
Page 543: Reception Error
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Stop bit: 1 bit One data frame RXDAn Start Parity Stop rxd_in Start Parity Stop UARTAn_RXI RXBAn Writing to RXBAn Stop bit: 2 bits One data frame RXDAn Start Parity Stop Stop...
Page 544: Receive Data Noise Filter
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) When ASIMAn0.ISRMA = 0, the reception error interrupt is separated from UARTAn_RXI. Reception is completed without an error. Reception is completed with an error. UARTAn_RXI UARTAn_RXI UARTAn_ERRI UARTAn_ERRI When ASIMAn0.ISRMA = 1, the reception error interrupt is included in UARTAn_RXI.
Page 545: Baud Rate Calculation
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) When bit 7 (EN) = 1 in the operation mode setting register 00 (ASIMA00), the UARTA0 operation clock (f ) is supplied UTA0 to each module. When ASIMA00.EN = 0, the UARTA0 operation clock is fixed to low level.
Page 546 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Error = − 1] × 100[%] Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) Note: Keep the baud rate error during transmission to within the permissible error range on the reception side.
Page 547 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Table 23.10 Set data of baud rate generator (2/4) (2 of 2) In operation with MOCO = 4 MHz (UTA0CK.SEL[1:0] = 11b) No division ×1/2 ×1/4 ×1/8 ×1/16 ×1/32 ×1/64 Desired (UTA0CK.CK[3: (UTA0CK.CK[3:...
Page 548 RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) Table 23.12 Set data of baud rate generator (4/4) (2 of 2) In operation with FSXP = 32.768 kHz (UTA0CK.CK[3:0] = 1000b) Desired baud rate Error from the desired baud rate 2400 bps −2.48%...
Page 549: Usage Notes
RA0E1 User's Manual 23. Serial Interface UARTA (UARTA) BRmax = (FLmin/11) Brate −1 21k+1 FLmax = FL × 11 21k+1 ● Maximum permissible data frame length (FLmax) BRmin = (FLmax/11) Brate −1 ● Minimum permissible baud rate for reception on the transmitting side (BRmin) 21k−1...
Page 550: Cyclic Redundancy Check (Crc)
RA0E1 User's Manual 24. Cyclic Redundancy Check (CRC) Cyclic Redundancy Check (CRC) 24.1 Overview The Cyclic Redundancy Check (CRC) generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be selected LSB-first communication. Additionally, two CRC-generation polynomials (16-bit CRC-CCITT and 32-bit CRC-32) are available.
Page 551: Crcdir/Crcdir_By : Crc Data Input Register
RA0E1 User's Manual 24. Cyclic Redundancy Check (CRC) Symbol Function GPS[2:0] CRC Generating Polynomial Switching 0 1 1: 16-bit CRC-CCITT (X + 1) 1 0 0: 32-bit CRC-32 (X + X + 1) Others: No calculation is executed — These bits are read as 0. The write value should be 0.
Page 552: Cyclic Redundancy Check (Crc)
RA0E1 User's Manual 24. Cyclic Redundancy Check (CRC) 24.3 Operation 24.3.1 Basic Operation The CRC calculator generates CRC codes for use in LSB-first. The following examples show CRC code generation for input data (0xF0) using the 16-bit CRC-CCITT generating polynomial (X + 1).
Page 553: Usage Notes
RA0E1 User's Manual 24. Cyclic Redundancy Check (CRC) 1. 8-bit serial reception (LSB-first) CRC code Data Input 2. Write 0x83 to the CRC Control Register 0 (CRCCR0) CRCCR0 CRCDOR_HA Clear CRCDOR/CRCDOR_HA 3. Write 0xF0 to the CRC Data Input Register (CRCDIR_BY)
Page 554 RA0E1 User's Manual 24. Cyclic Redundancy Check (CRC) When transmitting 32-bit data (for operation executed on 8 bits in parallel) 1. CRC code After specifying the method for generation calculation, write data to CRCDIR in order of (1), (2), (3), and (4).
Page 555: Bit A/D Converter (Adc12)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) 12-bit A/D Converter (ADC12) This is the ADC_D version of the ADC12 peripheral module. ADC_D is referred to as ADC12 in this chapter. 25.1 Overview The A/D converter is used to convert analog input signals into digital values, and is configured to control up to 10 channels of A/D converter analog inputs (AN000 to AN007, AN021 and AN022).
Page 556 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.1 ADC12 specifications (2 of 2) Parameter Specifications Reference voltage ● VREFH0, VCC, or internal reference voltage (BGR) (external reference voltage or output voltage from reference voltage generation circuit) can be selected as the analog reference voltage.
Page 557 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Selector Selector Selector Note: n = 0 to 3 Note: Analog input pins in this figure are for a 32-pin product. Note 1. For details about the internal reference voltage, see section 31, Electrical Characteristics.
Page 558 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) These are the analog input pins of the 10 channels of the A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
Page 559: Registers To Control The A/D Converter
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) In addition to VREFH0, it is possible to select V or the internal reference voltage as the ‘+’ side reference voltage of the A/D converter. Note 1. For details about the internal reference voltage, see section 31, Electrical Characteristics TA = -40 to +105°C.
Page 560 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Symbol Function ADMD Specification of the A/D conversion channel selection mode 0: Select mode 1: Scan mode ADCS A/D conversion operation control 0: Stops conversion operation [When read] ● Conversion is stopped or in standby...
Page 561 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.5 Conditions for setting and clearing the ADCS bit A/D conversion mode Set conditions Clear conditions Software trigger no- Select mode Sequential When 1 is written to When 0 is written to ADCS...
Page 562 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) ADCE ADCE = 0 Conversion Conversion Conversion stopped stopped operation Conversion start time A/D power supply stabilization wait time Interrupt output delay time Conversion Software trigger time wait mode (One-shot ADCS conversion...
Page 563 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) ADCE Conversion Conversion Conversion Conversion standby operation stopped standby Conversion start time Conversion start delay time Interrupt output delay time Conversion Software trigger time no-wait mode (One-shot ADCS conversion mode) Automatically cleared upon...
Page 564 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.6 Settings of conversion start time (2 of 2) ADM1 ADM0 Conversion start time (number of PCLKB clock) Conversion Software trigger no-wait mode/ Software trigger wait mode/ clock (f ADSLP FR[2:0]...
Page 565 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.8 Conversion start delay time, A/D power supply stabilization wait time, and interrupt output delay time (2 of 2) A/D power supply Conversion start stabilization wait delay time time (number (number of f...
Page 566 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.9 A/D conversion time in Normal mode 1 and 2 (2 of 2) A/D conversion time [µs] Select mode Scan mode Wait Wait PCLKB Conversion Voltage No-wait mode No-wait mode condition clock (f ADM0.LV[1:0]...
Page 567 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.10 A/D conversion time in Low voltage mode 1 and 2 (1 of 2) A/D conversion time [µs] Select mode Scan mode Wait Wait PCLKB Conversion condition Voltage No-wait mode No-wait...
Page 568 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.10 A/D conversion time in Low voltage mode 1 and 2 (2 of 2) A/D conversion time [µs] Select mode Scan mode Wait Wait PCLKB Conversion condition Voltage No-wait mode No-wait...
Page 569: Adm1 : A/D Converter Mode Register 1
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Note: Rewrite the FR[2:0], LV[1:0] bits to different values while conversion is stopped (ADCS = 0, ADCE = 0). The FR[2:0], and LV[1:0] bits should be changed at least 0.2 µs after conversion stops (ADCS = 0, ADCE = 0).
Page 570: Adm2 : A/D Converter Mode Register 2
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Symbol Function ADSCM Specification of the A/D Conversion Mode 0: Sequential conversion mode 1: One-shot conversion mode ADTMD[1:0] Selection of the A/D Conversion Trigger Mode 1 0: Hardware trigger no-wait mode 1 1: Hardware trigger wait mode Others: Software trigger no-wait mode or software trigger wait mode Note 1.
Page 571 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) This register is used to select the ‘+’ side and ‘-’ side reference voltages of the A/D converter, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the Snooze mode.
Page 572: Adcr/Adcrn: 12-Bit Or 10-Bit A/D Conversion Result Register N (N = 0 To 3)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) ADREFM bit (Selection of the ‘-’ Side Reference Voltage of the A/D Converter) This bit is used for selection of the ‘-’ side reference voltage of the 12-bit A/D converter. ADREFP[1:0] bits (Selection of the ‘+’ Side Reference Voltage Source of the A/D Converter) These bits are used for selection of the ‘+’...
Page 573: Adcrh/Adcrnh : 8-Bit A/D Conversion Result Register N (N = 0 To 3)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Note: The contents of the ADCRn register may become undefined when writing to any of the following registers. ● A/D converter mode register 0 (ADM0) ● Analog input channel specification register (ADS) Read the conversion result following conversion completion before writing to any of these registers.
Page 574 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.12 Input source selection by ADS[4:0] bits and ADISS bit in select mode ADISS ADS[4:0] Analog input channel Input source 00000b AN000 P010 00001b AN001 P011 00010b AN002 P008 00011b AN003...
Page 575: Adul : Conversion Result Comparison Upper Limit Setting Register
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) 25.2.7 ADUL : Conversion Result Comparison Upper Limit Setting Register Base address: ADC_D = 0x400A_1800 Offset address: 0x0111 Bit position: Bit field: Value after reset: Symbol Function Setting the Upper Limit for A/D Conversion Results This register is used to specify the setting for checking the upper limit of the A/D conversion results.
Page 576: A/D Converter Operations
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Symbol Function ADTES[1:0] Selection of A/D Conversion Target for Testing 0 0: ANxxx, temperature sensor output voltage or internal reference voltage (Set by analog input channel specification register (ADS)) 1 0: The ‘-’ side reference voltage (selected by the ADREFM bit of the ADM2 register) 1 1: The ‘+’...
Page 577: Input Voltage And Conversion Results
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) ● ADCRnH register (8 bits): Store 8-bit A/D conversion value Note: : The ‘+’ side reference voltage of the A/D converter. This can be selected from VREFH0, the internal reference voltage, and V...
Page 578: A/D Converter Operation Modes
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) ADCRn 4095 0x0FFF 4094 0x0FFE 4093 0x0FFD A/D conversion result 0x0003 0x0002 0x0001 0x0000 8187 4094 8189 4095 8191 8192 8192 4096 8192 4096 8192 4096 8192 4096 8192 4096 Input voltage/AV Figure 25.7...
Page 579: Software Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Figure 25.8 shows the example of software trigger no-wait mode (select mode, sequential conversion mode) operation timing. ADCE is set to 1. <1> ADCE is cleared to 0. <8> ADCE A hardware trigger...
Page 580: Software Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <1> ADCE is set to 1. ADCE is cleared to 0.<8> ADCE ADCS is set to ADCS is ADCS is overwritten <4> <7> <2> <4> <2> <5> <2> <4> <2> ADCS is...
Page 581: Software Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <1> ADCE is set to 1. ADCE is cleared to 0.<8> ADCE ADCS is overwritten <6> ADCS is cleared <2> ADCS is set to 1 while in the <7> <4> A hardware trigger is...
Page 582: Software Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <1> ADCE is set to 1. ADCE is cleared to 0. <8> <4> ADCE ADCS is cleared ADCS is ADCS is overwritten ADCS is set to 1 while <2> <5> <7> <2>...
Page 583: Software Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <1> ADCE = 0 ADCE ADCS is cleared to 0 <2> ADCS is overwritten <4> <6> A hardware trigger is <7> ADCS is set to 1 while in the during A/D conversion with 1 during A/D conversion standby state.
Page 584: Software Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <1> ADCE = 0 ADCE ADCS is set to 1 A hardware trigger ADCS is cleared to 0 <2> <2> <5> ADCS is overwritten <2> <8> <7> <3> <4> <2> ADCS is <4>...
Page 585: Software Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <1> ADCE = 0 ADCE <6> A hardware trigger is ADCS is cleared to 0 ADCS is set to 1 while in the ADCS is overwritten with 1 <7> <2> <4> generated (and ignored).
Page 586: Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <1> ADCE = 0 ADCE <4> ADCS is overwritten <5> <2> ADCS is set to 1 while ADCS is cleared to 0 <7> <2> <4> <2> <8> A hardware trigger is ADCS is...
Page 587: Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) ADCE is cleared to 0. <9> <1> ADCE is set to 1. ADCE <2> ADCS is set to 1. A hardware trigger is <5> <3> A hardware trigger The trigger is not generated during A/D is generated.
Page 588: Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) ADCE is cleared to 0. <10> <1> ADCE is set to 1. ADCE <2> ADCS is set to 1. <6> A hardware trigger is <3> <3> <3> <3> <3> A hardware trigger...
Page 589: Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <1> ADCE is set to 1. ADCE is cleared to 0.<9> ADCE <2> ADCS is set to 1. A hardware trigger is <5> <3> A hardware trigger generated during A/D is generated.
Page 590: Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Figure 25.19 shows the example of hardware trigger no-wait mode (scan mode, one-shot conversion mode) operation timing. <1> ADCE is set to 1. ADCE is cleared to 0. <10> <2> ADCS is set to 1.
Page 591: Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <1> ADCE is set to 1. <8> ADCE is set to 0. ADCE A hardware trigger is <4> The trigger <2> A hardware trigger generated during A/D Trigger is not standby is generated.
Page 592: Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) ADCE is <9> <1> ADCE is set to 1. set to 0. ADCE <5> A hardware trigger is Trigger A hardware trigger <2> <2> <2> <2> <2> The trigger is not generated during A/D standby is generated.
Page 593: Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) ADCE is <1> ADCE is set to 1. <8> set to 0. ADCE A hardware trigger is <4> <2> A hardware trigger Trigger generated during A/D The trigger is generated. standby is not conversion operation.
Page 594: A/D Converter Setup Procedure
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <1> ADCE is set to 1. ADCE is <9> set to 0. A hardware trigger is <5> ADCE A hardware trigger <2> <2> <2> generated during A/D <2> Trigger is generated. conversion operation.
Page 595 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.14 Setting up software trigger no-wait mode Step Process Detail Setting up <1> MSTPCRD register setting The MSTPD16 bit of the MSTPCRD register is set to 0, and Software Trigger supplying the clock starts.
Page 596: Setting Up Software Trigger Wait Mode
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) 25.6.2 Setting up Software Trigger Wait Mode Table 25.15 shows the setup steps in software trigger wait mode. Table 25.15 Setting up software trigger wait mode Step Process Detail Setting up <1>...
Page 597: Setting Up Hardware Trigger No-Wait Mode
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Note 1. Depending on the settings of the ADRCK bit, ADUL and ADLL registers, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCRn or ADCRnH register.
Page 598 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.16 Setting up hardware trigger no-wait mode Step Process Detail Setting up <1> MSTPCRD register setting The MSTPD16 bit of the MSTPCRD register is set to 0, and Hardware Trigger supplying the clock starts.
Page 599: Setting Up Hardware Trigger Wait Mode
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) 25.6.4 Setting up Hardware Trigger Wait Mode Table 25.17 shows the setup steps in hardware trigger wait mode. Table 25.17 Setting up hardware trigger wait mode Step Process Detail Setting up <1>...
Page 600: Example Of Using The Adc12 When Selecting The Temperature Sensor Output Voltage Or Internal Reference Voltage, And Software Trigger No-Wait Mode And One-Shot Conversion Mode
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) 25.6.5 Example of Using the ADC12 when Selecting the Temperature Sensor Output Voltage or Internal Reference Voltage, and Software Trigger No-wait Mode and One-shot Conversion Mode Table 25.18 shows the setup steps When Temperature Sensor Output Voltage and Internal Reference Voltage Is Selected.
Page 601 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.19 Setting up test mode Step Process Detail Setting up <1> MSTPCRD register setting The MSTPD16 bit of the MSTPCRD register is set to 0, and Test Mode supplying the clock starts.
Page 602: Snooze Mode Function
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) 25.7 Snooze Mode Function In Snooze mode, A/D conversion is triggered by inputting a hardware trigger in the Software Standby mode. Normally, A/D conversion is stopped while in the Software Standby mode, but, by using the Snooze mode function, A/D conversion can be performed without operating the CPU.
Page 603: If No Interrupt Is Generated After A/D Conversion Ends
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) mode release) of the A/D converter mode register 2 (ADM2). If the AWC bit is left set to 1, A/D conversion will not start normally in the subsequent Snooze or normal operation mode.
Page 604 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) RTC_ALM_OR_PRD Clock request signal (internal signal) The clock request signal is set to the low level. ADCS Conversion Channel 1 Channel 2 Channel 3 Channel 4 channels Comparison result from the A/D...
Page 605: Testing Of The A/D Converter
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) Table 25.20 Procedure for setting up Snooze mode (hardware trigger) (2 of 2) Step Process Detail Software Standby <7> Enter the Software Standby mode — mode Snooze mode <8> Hardware trigger generation...
Page 606: How To Read A/D Converter Characteristics Table
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) ADISS ADS[4:0] AN000/V REFH0 AN001/V REFL0 ANxxx ADTES[1:0] ANxxx Temperature sensor Internal reference voltage Positive reference voltage of A/D converter ADREFP[1:0] A/D converter Negative reference voltage of A/D converter ADREFM Figure 25.27 Configuration of testing of the A/D converter 25.9...
Page 607: Zero-Scale Error
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) 11...11b Ideal line Overall error 00...00b Analog input Figure 25.28 Overall error 11...11b Quantization error 1/2LSB 1/2LSB 00...00b Analog input Figure 25.29 Quantization error Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0……000b to 0……001b.
Page 608 RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) 111b Ideal line 011b 010b 001b Zero-scale error 000b Analog input (LSB) Figure 25.30 Zero-scale error Full-scale error 111b 110b 101b Ideal line 000b Analog input (LSB) Figure 25.31 Full-scale error 11...11b...
Page 609: Usage Notes
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) 11...11b Ideal 1LSB width Differential linearity error 00...00b Analog input Figure 25.33 Differential linearity error Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table.
Page 610: Noise Countermeasures
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) <2> Conflict between the conversion result being stored in the A/D conversion result register (ADCRn and ADCRnH) at the end of conversion and the write access to the A/D converter mode register 0 (ADM0) or analog input channel specification register (ADS) by instruction.
Page 611: Conversion Results Just After A/D Conversion Start
RA0E1 User's Manual 25. 12-bit A/D Converter (ADC12) To make sure that sampling is effective, however, we recommend using the converter with analog input sources that have output impedances no greater than 1 kΩ. If a source has a higher output impedance, lengthen the sampling time or connect a larger capacitor (with a value of about 0.1 µF) to the pin from among AN000 to AN007, AN021, and AN022 to which...
Page 612: Temperature Sensor (Tsn)
● V2: Voltage output by the temperature sensor on measurement of T2 (V) ● Slope: Temperature gradient of the temperature sensor (V / °C), slope = (V2 - V1) / (T2 -T1) Characteristics vary between sensors, so Renesas recommends measuring two different sample temperatures as follows: R01UH1040EJ0110 Rev.1.10...
Page 613: Procedures For Using The Temperature Sensor
RA0E1 User's Manual 26. Temperature Sensor (TSN) 1. Use the 12-bit A/D converter to measure the voltage V1 output by the temperature sensor at temperature T1. 2. Again use the 12-bit A/D converter to measure the voltage V2 output by the temperature sensor at a different temperature T2.
Page 614: Sram
RA0E1 User's Manual 27. SRAM SRAM 27.1 Overview The MCU provides an on-chip, high-density SRAM module with parity-bit checking. Parity check is performed on the all SRAM areas. Table 27.1 lists the SRAM specifications. Table 27.1 SRAM specifications Parameter Description...
Page 615: Operation
RA0E1 User's Manual 27. SRAM Symbol Function SRAMPRCR Register Write Control 0: Disable writes to protected registers 1: Enable writes to protected registers KW[6:0] Write Key Code These bits enable or disable writes to the SRAMPRCR bit SRAMPRCR bit (Register Write Control) The SRAMPRCR bit controls the write mode of the PARIOAD register.
Page 616 RA0E1 User's Manual 27. SRAM <MAIN processing> <NMI processing> Start of Check RPERF Initial setting Initial setting (parity reset) (parity NMI) Check SRAM Check SRAM Parity error generated Parity error generated Normal SRAM failure Reset generated operation processing Note 1. RPERF: Internal Reset Request by RAM Parity Error Flag (RESF.RPERF bit) Figure 27.1...
Page 617: Sram Error Sources
RA0E1 User's Manual 27. SRAM <MAIN processing> <NMI processing> Start of check Initial setting (parity NMI) Check SRAM Parity error generated RPEST Check SRAM RETURN RPEST Normal SRAM failure operation processing Note 1. RPEST: SRAM Parity Error Interrupt Status Flag (NMISR.RPEST bit) Figure 27.2...
Page 618: Low-Power Function
CPU prefetches data from an SRAM area that is not initialized, a parity error might occur. Initialize the additional 2-byte area from the end address of a program with a 4-byte boundary. Renesas recommends using the NOP instruction for data initialization.
Page 619: Flash Memory
RA0E1 User's Manual 28. Flash Memory Flash Memory 28.1 Overview The MCU provides up to 64-KB code flash memory and 1-KB data flash memory. The Flash Control Block (FCB) controls ® the programming commands. This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc.
Page 620: Memory Structure
RA0E1 User's Manual 28. Flash Memory 28.2 Memory Structure Figure 28.2 shows the mapping of the code flash memory, and Table 28.2 shows the read and programming and erasure (P/E) addresses of the code flash memory. The user area of the code flash memory is divided into 2-KB blocks that serve as the units of erasure.
Page 621: Register Descriptions
RA0E1 User's Manual 28. Flash Memory Table 28.3 Read and P/E addresses of the data flash memory Size of data flash memory Read address P/E address Number of blocks 1-KB 0x4010_0000 to 0x4010_03FF 0xFE00_0000 to 0xFE00_03FF 0, 1, 2, 3 28.3...
Page 622: Fpr : Protection Unlock Register
RA0E1 User's Manual 28. Flash Memory [Clearing conditions] ● Data is written by byte access ● A value other than 0xAA is set to the FEKEY[7:0] bits and written to the FENTRYR register ● Set 0xAA00 to the FENTRYR register ●...
Page 623: Fpsr : Protection Unlock Status Register
RA0E1 User's Manual 28. Flash Memory 28.3.4 FPSR : Protection Unlock Status Register Base address: FLCN = 0x407E_C000 Offset address: 0x0184 Bit position: Bit field: — — — — — — — PERR Value after reset: Symbol Function PERR Protect Error Flag...
Page 624: Fisr : Flash Initial Setting Register
RA0E1 User's Manual 28. Flash Memory section 28.3.3. FPR : Protection Unlock Register for the procedure to unlock the protection. FMS0 bit, FMS1 bits (Flash Operating Mode Select 0, Flash Operating Mode Select 1) These bits set the operating mode of the flash memory.
Page 625: Fresetr : Flash Reset Register
RA0E1 User's Manual 28. Flash Memory Table 28.4 Frequency settings Flash-IF clock Flash-IF clock Flash-IF clock frequency frequency frequency [MHz] PCKA[4:0] [MHz] PCKA[4:0] [MHz] PCKA[4:0] 11111b 10111b 10011b 10010b 10001b 10000b 01111b 01110b 01101b 01100b 01011b 01010b 01001b 01000b 00111b...
Page 626: Fasr : Flash Area Select Register
RA0E1 User's Manual 28. Flash Memory 28.3.8 FASR : Flash Area Select Register Base address: FLCN = 0x407E_C000 Offset address: 0x0104 Bit position: Bit field: — — — — — — — Value after reset: Symbol Function Extra Area Select 0: User area or data area 1: Extra area.
Page 627: Fexcr : Flash Extra Area Control Register
RA0E1 User's Manual 28. Flash Memory Verifies whether the flash memory is the blank state (not to be programmed) from the start address pointed by the FSARH and FSARL registers to the end address pointed by the FEARH and FEARL registers. The blank check command is allowed to execute within the region of flash memory.
Page 628 RA0E1 User's Manual 28. Flash Memory CMD[2:0] bits (Software Command Setting) The CMD[2:0] bits select the software command from the: ● Startup area selection and security setting ● Access window information program ● OCDID program. The following information describes the function of each software command.
Page 629: Fsarh : Flash Processing Start Address Register H
RA0E1 User's Manual 28. Flash Memory [OCDID1-4 program] These commands set the OCDID[127:0] bits. Table 28.7 OCDID settings Command OCDID FWBH0 FWBL0 OCDID1 program OCDID [31:0] OCDID [31:16] OCDID [15:0] OCDID2 program OCDID [63:32] OCDID [63:48] OCDID [47:32] OCDID3 program...
Page 630: Fsarl : Flash Processing Start Address Register L
RA0E1 User's Manual 28. Flash Memory Symbol Function 15:0 FSARH[15:0] Flash Processing Start Address H Flash Processing Start Address upper 16 bits See FSARL for details. Note: Set or clear this register only in P/E mode. The write value should be 0 for b8 to b4, and those bits are read as 0.
Page 631: Fwbl0 : Flash Write Buffer Register L0
RA0E1 User's Manual 28. Flash Memory Symbol Function 15:0 FEARL[15:0] Flash Processing End Address L Flash processing end address lower 16 bits Note: Set or clear this register only in P/E mode. The FEARH and FEARL registers set the end address of the blank check and the block erase command. When the FEARH and FEARL registers are read while executing a software command set by the FEXCR register, an undefined value is read.
Page 632: Fstatr1 : Flash Status Register 1
RA0E1 User's Manual 28. Flash Memory 28.3.17 FSTATR1 : Flash Status Register 1 Base address: FLCN = 0x407E_C000 Offset address: 0x012C Bit position: EXRD Bit field: FRDY — — — — — — Value after reset: Symbol Function — These bits are read as 0.
Page 633: Feamh : Flash Error Address Monitor Register H
RA0E1 User's Manual 28. Flash Memory ERERR flag (Erase Error Flag) The value of the ERERR bit is undefined when the FCR.STOP bit is set to 1 (processing is forcibly stopped) during erasure. PRGERR flag (Program Error Flag) The PRGERR bit is set when the program command of the FCR register or each command of the FEXCR register is abnormally terminated.
Page 634: Feaml : Flash Error Address Monitor Register L
RA0E1 User's Manual 28. Flash Memory 28.3.20 FEAML : Flash Error Address Monitor Register L Base address: FLCN = 0x407E_C000 Offset address: 0x01E0 Bit position: Bit field: FEAML[15:0] Value after reset: Symbol Function 15:0 FEAML[15:0] Flash Error Address Monitor Register L Flash error address monitor lower 16 bits The error address is withdrawn from the FEAMH and FEAML registers after a software command execution.
Page 635: Fawemr : Flash Access Window End Address Monitor Register
RA0E1 User's Manual 28. Flash Memory Symbol Function 10:0 FAWS[10:0] Access Window Start Address This register is used to confirm the set value of the access window start address used for area protection 14:11 — These bits are read as 0.
Page 636: Mcuver : Mcu Version Register
RA0E1 User's Manual 28. Flash Memory The PNRn is a read-only register that stores a 16-byte part numbering. The PNRn register should be read in 32-bit units. Each byte corresponds to the ASCII code representation of the product part number as detailed in product list.
Page 637: Id Code Protection
RA0E1 User's Manual 28. Flash Memory Reset state Normal operating mode On-chip debug mode Figure 28.4 Mode transitions associated with flash memory The flash memory areas where programming and erasure are permitted and where the boot program executes at a reset, differ with the mode.
Page 638: Overview Of Functions
RA0E1 User's Manual 28. Flash Memory Table 28.13 Specifications for ID code protection Operations on connection with the Operating mode on boot up ID code State of protection programmer or on-chip debugger On-chip debug mode 0xFF, …, 0xFF (all bytes 0xFF)
Page 639: Configuration Area Bit Map
RA0E1 User's Manual 28. Flash Memory Table 28.15 Basic functions Availability Function Functional overview Self-programming SWD programming Blank check Checks a specified block to ensure that writing to it Supported Supported has not already proceeded. Block erasure Erases the memory contents in the specified block...
Page 640: Startup Area Select
RA0E1 User's Manual 28. Flash Memory Base R-address: 0x0101_0000 offset +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1...
Page 641: Programming Commands
RA0E1 User's Manual 28. Flash Memory The access window is specified in both the FAWS [10:0] and FAWE [10:0] bits. See section 6.2.3. AWS : Access Window Setting Register. Setting of the FAWE[10:0] and FAWS[10:0] bits in various conditions is described as follows: ●...
Page 642: Area Protection
RA0E1 User's Manual 28. Flash Memory Figure 28.8 shows an overview of the Startup Program Protection. In this figure, the default area indicates the 8-KB region from the start address and the alternate area indicates the next 8-KB region. Address...
Page 643: Self-Programming
RA0E1 User's Manual 28. Flash Memory Address The address : That is set to the FWBH0 Disabled register in executing the Block 8 access window information 0x0000_4000 program command (the next Block 7 0x0000_3FFF block of the end block of the...
Page 644: Background Operation
RA0E1 User's Manual 28. Flash Memory Internal SRAM Internal SRAM or code flash memory User’s programming program User’s programming program Programming command Programming command Execution of programming command Execution of programming command Information on Information on functions functions flash memory...
Page 645: Read Mode
RA0E1 User's Manual 28. Flash Memory Reset Code Flash : read mode Data Flash Data Flash : access disable Access Disable Mode DFLCTL = 0x01 DFLCTL = 0x00 FENTRYR = 0xAA80 FPMCR ← 0x10/0x50 Code Flash : read mode Code Flash/Data Flash...
Page 646: Software Command Usage
RA0E1 User's Manual 28. Flash Memory Table 28.18 Software commands Command Function Program Code flash programming (4 bytes) Data flash programming (1 byte) Block erase Code flash/data flash erasure Blank check Check whether the specified area is blank. Confirm that data is not programmed in the area. This command does not guarantee whether the area remains erased.
Page 647 RA0E1 User's Manual 28. Flash Memory Start in Code Flash read mode Set Code Flash P/E mode Write to FENTRYR register When setting the FENTRYR.FENTRY0 bit to 1: Write 0xAA01 When setting the FPMCR register to 0x02: Write 0xA5 to the FPR register...
Page 648 RA0E1 User's Manual 28. Flash Memory Switching the Code Flash or Data Flash P/E Mode to Read Mode Start in Code Flash P/E mode When setting the FPMCR register to 0x08: Write 0xA5 to the FPR register Write 0x08 to FPMCR register...
Page 649 RA0E1 User's Manual 28. Flash Memory Start in Data Flash P/E mode When setting the FPMCR register to 0x08: Write 0xA5 to the FPR register Write 0x08 to FPMCR register Write 0x08 to the FPMCR register Write 0xF7 to the FPMCR register...
Page 650 RA0E1 User's Manual 28. Flash Memory Start in Code Flash P/E mode If the frequency is Set frequency in the same value as FISR.PCKA bit the current one, it is possible to skip this step. Set programming address in FSARH and FSARL registers...
Page 651 RA0E1 User's Manual 28. Flash Memory Start in Data Flash P/E mode If the frequency is Set frequency in the same value as FISR.PCKA bit the current one, it is possible to skip this step. Set programming address in FSARH and FSARL registers...
Page 652 RA0E1 User's Manual 28. Flash Memory Start in Code Flash P/E mode If the frequency is Set frequency in the same value as FISR.PCKA bit the current one, it is possible to skip this step. Set start address of the target...
Page 653 RA0E1 User's Manual 28. Flash Memory Start in Data Flash P/E mode If the frequency is Set frequency in the same value as FISR.PCKA bit the current one, it is possible to skip this step. Set start address of the target...
Page 654 RA0E1 User's Manual 28. Flash Memory Start in Code Flash P/E mode If the frequency is the same Set frequency in value as the current one, FISR.PCKA bit it is possible to skip this step. Set start address of the target...
Page 655 RA0E1 User's Manual 28. Flash Memory Start in Data Flash P/E mode If the frequency is the same Set frequency in value as the current one, FISR.PCKA bit it is possible to skip this step. Set start address of the target...
Page 656 RA0E1 User's Manual 28. Flash Memory Start in Code Flash P/E mode If the frequency is the same Set frequency in value as the current one, FISR.PCKA bit it is possible to skip this step. FASR.EXS bit = 1 Set Programming data in...
Page 657: Reading The Flash Memory
RA0E1 User's Manual 28. Flash Memory Set the FSPR bit after programing of the startup area information and the access window information. If the FSPR bit is set before programing of the startup area information and the access window information, the programming cannot be performed because of the security function in the FSPR.
Page 658: Usage Notes
RA0E1 User's Manual 28. Flash Memory 28.12 Usage Notes 28.12.1 Erase Suspended Area Data in areas where an erase operation is suspended is undefined. To avoid malfunctions caused by reading undefined data, do not execute commands and read data in the area where erase operation is suspended.
Page 659: Flash-If Clock (Iclk) During Program/Erase
RA0E1 User's Manual 28. Flash Memory 28.12.9 Flash-IF clock (ICLK) during Program/Erase For programming/erasure by self-programming, it is necessary to specify an integer frequency by setting the Flash Initial Setting Register (FISR). R01UH1040EJ0110 Rev.1.10 Page 659 of 734 Dec 13, 2024...
Page 660: True Random Number Generator (Trng)
RA0E1 User's Manual 29. True Random Number Generator (TRNG) True Random Number Generator (TRNG) 29.1 Overview The true random number generator generates 32-bit random number seeds (which are true random numbers). The data generated by testing a seed itself and a random number which is generated from a seed (using the continuous random number generator test prescribed in NIST FIPS140-2) are the same by a fixed probability according to the bit length of the two generated random numbers.
Page 661: Trngscr1 : Trng Seed Command Register 1
RA0E1 User's Manual 29. True Random Number Generator (TRNG) Symbol Function SGCEN Seed Generation Circuit Enable 0: Seed generation circuit is disable. 1: Seed generation circuit is enable. — These bits are read as 0. The write value should be 0.
Page 662: Internal Voltage Regulator
RA0E1 User's Manual 30. Internal Voltage Regulator Internal Voltage Regulator 30.1 Overview The MCU includes one internal voltage regulator: ● Linear regulator (LDO) This regulator supplies voltage to all internal circuits and memory except for I/O and analog domains. 30.2 Operation Table 30.1...
Page 663: Electrical Characteristics
RA0E1 User's Manual 31. Electrical Characteristics Electrical Characteristics Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions: = VREFH0 = 1.6 to 5.5 V VSS = VREFL0 = 0 V, Ta = T Note 1. The typical condition is set to VCC = 3.3 V.
Page 664: Tj/Ta Definition
RA0E1 User's Manual 31. Electrical Characteristics Table 31.1 Absolute maximum ratings (2 of 2) Parameter Symbol Value Unit High-level output current P100 to P103, P108 Per pin 1　 to P110, P112, P201 Total of all pins -100 to P207, P208, P300,...
Page 665: Oscillators Characteristics
RA0E1 User's Manual 31. Electrical Characteristics 31.2 Oscillators Characteristics 31.2.1 Main clock Oscillator Characteristics Table 31.4 Main clock oscillator characteristics Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Unit Test conditions Ceramic resonator 0.05...
Page 666: Dc Characteristics
RA0E1 User's Manual 31. Electrical Characteristics Table 31.6 On-chip oscillators characteristics (2 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Unit Test conditions Low-speed on-chip oscillator clock frequency —...
Page 667 RA0E1 User's Manual 31. Electrical Characteristics Table 31.8 I/O I Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Unit Test conditions Allowable low-level output Per pin for P100 to P103, —...
Page 668 RA0E1 User's Manual 31. Electrical Characteristics Table 31.9 I/O V (2 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Unit Test conditions Input voltage, low P100 to P103, Normal input —...
Page 669 RA0E1 User's Manual 31. Electrical Characteristics Table 31.10 I/O V (2 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Unit Test conditions Output voltage, low P100 to P103, P108 to —...
Page 670 RA0E1 User's Manual 31. Electrical Characteristics Table 31.11 I/O other characteristics (2 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Unit Test conditions Input leakage current, low P100 to P103, P108 to —...
Page 671: Operating And Standby Current
RA0E1 User's Manual 31. Electrical Characteristics 31.3.2 Operating and Standby Current Table 31.12 Operating and standby current (1) (1 of 2) Conditions: VCC = 1.6 to 5.5 V Test Parameter Symbol Unit Conditions Supply High- Normal All peripheral clocks ICLK = 32 MHz —...
Page 672 RA0E1 User's Manual 31. Electrical Characteristics Table 31.12 Operating and standby current (1) (2 of 2) Conditions: VCC = 1.6 to 5.5 V Test Parameter Symbol Unit Conditions Supply Subosc- Normal Peripheral clocks ICLK = 32.768 kHz Ta = -40°C —...
Page 673 RA0E1 User's Manual 31. Electrical Characteristics Table 31.13 Operating and standby current (2) Conditions: VCC = 1.6 to 5.5 V Parameter Symbol Unit Test conditions Supply Software Peripheral PSMCR.RA All SRAMs Ta = -40°C 0.20 µA — current Standby modules...
Page 674 RA0E1 User's Manual 31. Electrical Characteristics Table 31.14 Peripheral Functions Supply current Conditions: VCC = 1.6 to 5.5 V Test Parameter Symbol Typ Max Unit conditions Peripheral High-speed on chip oscillator operating OFS1.HOCOFRQ1[2:0] are 010b — µA — HOCO Functions...
Page 675: Thermal Characteristics
RA0E1 User's Manual 31. Electrical Characteristics When the low-speed on-chip oscillator (LOCO) is selected, I should be included in the supply current. LOCO When the Sub-clock oscillator (SOSC) is selected, I should be included in the supply current. SOSC Note 4. This current only flows to the 32-bit interval timer. It does not include the operating current of the low-speed on-chip oscillator (LOCO) or Sub-clock oscillator (SOSC).
Page 676: Ac Characteristics
RA0E1 User's Manual 31. Electrical Characteristics 31.4 AC Characteristics Table 31.16 AC characteristics Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Unit Test conditions Instruction cycle Main system clock High- 0.03125...
Page 677 RA0E1 User's Manual 31. Electrical Characteristics In normal operation During self programming 0.25 0.05 0.03125 0.01 Supply voltage V Figure 31.2 vs V in High-speed mode In normal operation During self programming 0.25 0.05 0.04167 0.01 Supply voltage V Figure 31.3...
Page 678 RA0E1 User's Manual 31. Electrical Characteristics In normal operation 0.05 0.01 Supply voltage V Figure 31.4 vs V in Low-speed mode Test points Figure 31.5 AC timing test points EXCLK Figure 31.6 External system clock timing R01UH1040EJ0110 Rev.1.10 Page 678 of 734...
Page 679: Reset Timing
RA0E1 User's Manual 31. Electrical Characteristics TI00 to TI07 TO00 to TO07 Figure 31.7 TI/TO timing IRQL IRQH IRQ0/NMI, IRQ1 to IRQ5 Figure 31.8 IRQ interrupt input timing 31.4.1 Reset Timing Table 31.17 Reset timing Test Parameter Symbol Unit conditions RES pulse width　...
Page 680 RA0E1 User's Manual 31. Electrical Characteristics RESWP Internal reset RESWT Figure 31.9 Reset input timing at power-on RESW Internal reset RESWT2 Figure 31.10 Reset input timing (1) Independent watchdog timer reset Software reset RESW2 Internal reset Figure 31.11 Reset input timing (2) R01UH1040EJ0110 Rev.1.10...
Page 681: Wakeup Time
RA0E1 User's Manual 31. Electrical Characteristics 31.4.2 Wakeup Time Table 31.18 Timing of recovery from low power modes (1) Test Parameter Symbol Unit conditions Recovery High-speed Crystal resonator System clock source — 1.64 — Figure 31.12 SBYMC time from mode...
Page 682 RA0E1 User's Manual 31. Electrical Characteristics Table 31.19 Timing of recovery from low power modes (2) Parameter Symbol Unit Test conditions Recovery Middle-speed Crystal System clock source — 1.64 — Figure 31.12 SBYMC time from mode resonator is main clock...
Page 683 RA0E1 User's Manual 31. Electrical Characteristics Oscillator ICLK Software Standby mode SBYMC, SBYEX, SBYMO SBYHO Oscillator ICLK Software Standby mode SBYSC SBYLO Figure 31.12 Software Standby mode cancellation timing Table 31.22 Timing of recovery from low power modes (5) Parameter...
Page 684: Peripheral Function Characteristics
RA0E1 User's Manual 31. Electrical Characteristics Oscillator ICLK Software Standby mode Snooze mode Figure 31.13 Recovery timing from Software Standby mode to Snooze mode 31.5 Peripheral Function Characteristics 31.5.1 Serial Array Unit (SAU) Table 31.23 In UART communications with devices operating at same voltage levels Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C...
Page 685 RA0E1 User's Manual 31. Electrical Characteristics 1/Transfer rate High-/low-bit width Baud rate error tolerance TXDq RXDq Figure 31.15 Bit width in the UART communications when interfacing devices operate at the same voltage level (reference) Note: ● q: UART number (q = 0 to 2), gh: Port number (gh = 100, 101, 109, 110, 212, 213) ●...
Page 686 RA0E1 User's Manual 31. Electrical Characteristics Table 31.25 In simplified SPI communications in the master mode with devices operating at same voltage levels with the internal SCKp clock Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C...
Page 687 RA0E1 User's Manual 31. Electrical Characteristics Table 31.26 In simplified SPI communications in the slave mode with devices operating at same voltage levels with the SCKp external clock Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C...
Page 688 RA0E1 User's Manual 31. Electrical Characteristics SCKp User device microcontroller Figure 31.16 Connection in the simplified SPI communications with devices operating at same voltage levels KCY1, 2 KL1, 2 KH1, 2 SCKp SIK1, 2 KSI1, 2 Input data KSO1, 2 Output data Figure 31.17...
Page 689 RA0E1 User's Manual 31. Electrical Characteristics KCY1, 2 KH1, 2 KL1, 2 SCKp SIK1, 2 KSI1, 2 Input data KSO1, 2 Output data Figure 31.18 Timing of serial transfer in the simplified SPI communications with devices operating at same voltage levels when SCRmn.DCP[1:0] = 01b or 10b Note: ●...
Page 690 RA0E1 User's Manual 31. Electrical Characteristics Table 31.27 In simplified IIC communications with devices operating at same voltage levels (1 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C High-speed mode...
Page 691 RA0E1 User's Manual 31. Electrical Characteristics Table 31.27 In simplified IIC communications with devices operating at same voltage levels (2 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C High-speed mode...
Page 692 RA0E1 User's Manual 31. Electrical Characteristics HIGH SCLr SDAr SU:DAT HD:DAT Figure 31.20 Timing of serial transfer in the simplified IIC communications with devices operating at same voltage levels Note: ● R [Ω]: Communication line (SDAr) pull-up resistance, C [F]: Communication line (SDAr, SCLr) load capacitance ●...
Page 693 RA0E1 User's Manual 31. Electrical Characteristics To set this operating clock, use the CKS bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 03, 10, 11) ● Communications by using P212 and P213 with devices operating at different voltage levels are not possible since P212PFS_A and P213PFS_A registers do not have PIM bit.
Page 694 RA0E1 User's Manual 31. Electrical Characteristics This value is the theoretical value of the relative difference between the transmission and reception sides. Note 7. This rate is calculated as an example when the conditions described in the Conditions column are met. See above to calculate the maximum transfer rate under conditions of the customer.
Page 695 RA0E1 User's Manual 31. Electrical Characteristics Table 31.30 In simplified SPI communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to SPI00) Conditions: VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C...
Page 696 RA0E1 User's Manual 31. Electrical Characteristics To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) Table 31.31 In simplified SPI communications in the master mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the internal SCKp clock (1)
Page 697 RA0E1 User's Manual 31. Electrical Characteristics Table 31.32 In simplified SPI communications in the master mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the internal SCKp clock (2) Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C...
Page 698 RA0E1 User's Manual 31. Electrical Characteristics Table 31.33 In simplified SPI communications in the master mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the internal SCKp clock (3) Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C...
Page 699 RA0E1 User's Manual 31. Electrical Characteristics ● p: Simplified SPI number (p = 00, 11, 20), m: Unit number, n: Channel number (mn = 00, 03, 10), gh: Port number (gh = 100 to 103, 109, 110, 112, 201, 212, 213, 407) ●...
Page 700 RA0E1 User's Manual 31. Electrical Characteristics KCY1 SCKp SIK1 KSI1 Input data KSO1 Output data Figure 31.25 Timing of serial transfer in the simplified SPI communications in the master mode with devices operating at different voltage levels when SCRmn.DCP[1:0] = 01b or 10b Note: ●...
Page 701 RA0E1 User's Manual 31. Electrical Characteristics Table 31.34 In simplified SPI communications in the slave mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the external SCKp clock Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C...
Page 702 RA0E1 User's Manual 31. Electrical Characteristics <Slave> SCKp User device microcontroller Figure 31.26 Connection in the simplified SPI communications with devices operating at different voltage levels Note: ● R [Ω]: Communication line (SOp) pull-up resistance, C [F]: Communication line (SOp) load capacitance, V...
Page 703 RA0E1 User's Manual 31. Electrical Characteristics KCY2 SCKp SIK2 KSI2 Input data KSO2 Output data Figure 31.28 Timing of serial transfer in the simplified SPI communications in the slave mode with devices operating at different voltage levels when SCRmn.DCP[1:0] = 01b or 10b Note: ●...
Page 704 RA0E1 User's Manual 31. Electrical Characteristics Table 31.35 Simplified IIC communications with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) (1 of 2) Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C...
Page 705 RA0E1 User's Manual 31. Electrical Characteristics Table 31.35 Simplified IIC communications with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) (2 of 2) Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C...
Page 706: Uart Interface (Uarta)
RA0E1 User's Manual 31. Electrical Characteristics HIGH SCLr SDAr SU:DAT HD:DAT Figure 31.30 Timing of serial transfer in the simplified IIC communications with devices operating at different voltage levels Note: ● R [Ω]: Communication line (SDAr, SCLr) pull-up resistance, C...
Page 707: I 2 C Bus Interface (Iica)
RA0E1 User's Manual 31. Electrical Characteristics 31.5.3 C Bus Interface (IICA) Table 31.37 C standard mode Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min. Typ. Max. Unit Test conditions SCLA0 clock frequency Standard mode: PCLKB ≥...
Page 708: Analog Characteristics
RA0E1 User's Manual 31. Electrical Characteristics Table 31.39 C fast mode plus Conditions: VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min. Typ. Max. Unit Test conditions SCLA0 clock frequency Fast mode plus: PCLKB ≥ 10 MHz —...
Page 709 RA0E1 User's Manual 31. Electrical Characteristics Table 31.40 A/D conversion characteristics in Normal modes 1 and 2 (2 of 2) Conditions: 2.4V ≤ VREFH0 ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Reference voltage range applied to the VREFH0 (ADVREFP[1:0] = 01b) and VREFL0 (ADVREFM = 1b).
Page 710 RA0E1 User's Manual 31. Electrical Characteristics Table 31.41 A/D conversion characteristics in Low-voltage modes 1 and 2 (1) (2 of 2) Conditions: 1.6 V ≤ VREFH0 ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Reference voltage range applied to the VREFH0 (ADVREFP[1:0] = 01b) and VREFL0 (ADVREFM = 1b).
Page 711 RA0E1 User's Manual 31. Electrical Characteristics Table 31.42 A/D conversion characteristics in Low-voltage modes 1 and 2 (2) (2 of 2) Conditions: 1.8 V ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Reference voltage range applied to the internal reference voltage (ADVREFP[1:0] = 10b) and VREFL0 (ADVREFM = 1b).
Page 712: Absolute Accuracy
RA0E1 User's Manual 31. Electrical Characteristics 0xFFF Full-scale error Integral nonlinearity error (INL) A/D converter output code Ideal line of actual A/D conversion characteristic Actual A/D conversion characteristic Ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D...
Page 713: Full-Scale Error
RA0E1 User's Manual 31. Electrical Characteristics Full-scale error Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code. 31.6.2 Temperature Sensor/Internal Reference Voltage Characteristics Table 31.44 Temperature sensor/internal reference voltage characteristics Conditions: 1.8 V ≤...
Page 714: Lvd Characteristics
RA0E1 User's Manual 31. Electrical Characteristics 31.6.4 LVD Characteristics Table 31.46 LVD0 characteristics Conditions: VPDR ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Unit Test Conditions Detection voltage Supply voltage level 3.84 3.96...
Page 715 RA0E1 User's Manual 31. Electrical Characteristics Table 31.47 LVD1 characteristics (2 of 2) Conditions: VPDR ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Unit Test Conditions Detection voltage Supply voltage level 2.25 2.30...
Page 716: Power Supply Voltage Rising Slope Characteristics
Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. The listed numbers of times apply when using the flash memory programmer and self-programming. Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation.
Page 717: Serial Wire Debug (Swd)
RA0E1 User's Manual 31. Electrical Characteristics Table 31.51 Code flash memory characteristics Conditions: 1.8 V ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol ICLK = 1 MHz ICLK = 2 MHz, 3 MHz 4 MHz ≤...
Page 718 RA0E1 User's Manual 31. Electrical Characteristics Table 31.53 SWD characteristics (1) (2 of 2) Conditions: VCC = 2.4 to 5.5 V Parameter Symbol Unit Test conditions SWDIO setup time — — Figure 31.38 SWDS SWDIO hold time — — SWDH SWDIO data delay time —...
Page 719 RA0E1 User's Manual 31. Electrical Characteristics SWCLK SWDS SWDH SWDIO (Input) SWDD SWDIO (Output) SWDD SWDIO (Output) SWDD SWDIO (Output) Figure 31.38 SWD input/output timing R01UH1040EJ0110 Rev.1.10 Page 719 of 734 Dec 13, 2024...
Page 720: Appendix 1. Port States In Each Processing Mode
RA0E1 User's Manual Appendix 1. Port States in each Processing Mode Appendix 1. Port States in each Processing Mode Table A1.1 Port states in each processing mode (1 of 3) Port name Reset Software Standby Mode P008/AN002 Hi-Z Keep-O P009/AN003...
Page 721 RA0E1 User's Manual Appendix 1. Port States in each Processing Mode Table A1.1 Port states in each processing mode (2 of 3) Port name Reset Software Standby Mode P110/IRQ3_B/TI01_A/TO01_A/RXD2_A/SI20_A/SDA20_A/RXDA0_C/SCLA0_C Hi-Z [IRQ3_B selected] IRQ3_B input [RXDA0_C selected] RXDA0_C input [SCLA0_C selected]...
Page 722 RA0E1 User's Manual Appendix 1. Port States in each Processing Mode Table A1.1 Port states in each processing mode (3 of 3) Port name Reset Software Standby Mode Hi-Z P213/X2/(XCOUT )/EXCLK/IRQ0_B/TI00_A/TI02_B/TO02_B/TXD1_A/SO11_A/ [Sub-clock Oscillator selected] TXDA0_B/SDAA0_B Sub-clock Oscillator is operating； [IRQ0_B selected]...
Page 723: Appendix 2. Package Dimensions
RA0E1 User's Manual Appendix 2. Package Dimensions Appendix 2. Package Dimensions Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas Electronics Corporation website. JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP32-7x7-0.80...
Page 724 RA0E1 User's Manual Appendix 2. Package Dimensions Figure A2.2 HWQFN 32-pin R01UH1040EJ0110 Rev.1.10 Page 724 of 734 Dec 13, 2024...
Page 725 RA0E1 User's Manual Appendix 2. Package Dimensions JEITA Package Code RENESAS Code MASS(Typ.) [g] P-HWQFN24-4x4-0.50 PWQN0024KG-A 0.04 Figure A2.3 HWQFN 24-pin R01UH1040EJ0110 Rev.1.10 Page 725 of 734 Dec 13, 2024...
Page 726 ” does not include tr 1.15 0.65 0.12 0.10 0.22 0.05 0.05 0.15 0.02 0.50 0.20 0.10 0 to 10 2012 Renesas Electronics Corporation. All rights reserved. Figure A2.4 LSSOP 20-pin R01UH1040EJ0110 Rev.1.10 Page 726 of 734 Dec 13, 2024...
Page 727 RA0E1 User's Manual Appendix 2. Package Dimensions JEITA Package code MASS(TYP.)[g] RENESAS code P-HWQFN016-3x3-0.50 PWQN0016KD-A 0.02 aaa C INDEX AREA (D/2 X E/2) aaa C ccc C Dimension in Millimeters Reference SEATING PLANE (A3) Symbol Min. Nom. Max. b(16X) C A B －...
Page 728: Appendix 3. I/O Registers
RA0E1 User's Manual Appendix 3. I/O Registers Appendix 3. I/O Registers This appendix describes I/O register addresses, access cycles, and reset values by function. Peripheral Base Addresses This section provides the base addresses for peripherals described in this manual. Table A3.1 shows the name, description, and the base address of each peripheral.
Page 729 RA0E1 User's Manual Appendix 3. I/O Registers ● Registers are grouped by associated module. ● The number of access cycles indicates the number of cycles based on the specified reference clock. ● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations cannot be guaranteed.
Page 730: Appendix 4. Peripheral Variant
RA0E1 User's Manual Appendix 4. Peripheral Variant Appendix 4. Peripheral Variant Table A4.1 shows the correspondence between the module name used in this manual and the Peripheral Variant. Table A4.1 Module name vs Peripheral Variant Module name Peripheral Variant ADC12...
Page 731: Revision History
RA0E1 User's Manual Revision History Revision History Revision 1.00 — January 31, 2024 Initial release Revision 1.10 — December 13, 2024 Preface: ● Updated 9. Abbreviations. 1. Overview: ● Updated Figure 1.1 Block diagram. ● Updated Figure 1.2 Part numbering scheme.
Page 732 RA0E1 User's Manual Revision History Revision 1.10 — December 13, 2024 31. Electrical Characteristics: ● Updated Table 31.1 Absolute maximum ratings. ● Updated 32.2.3 On-chip Oscillators Characteristics. ● Updated Table 31.11 I/O other characteristics. ● Updated Table 31.14 Peripheral Functions Supply current.
Page 733 RA0E1 Group User’s Manual: Hardware Publication Date: Rev.1.10 Dec 13, 2024 Rev.1.00 Jan 31, 2024 Published by: Renesas Electronics Corporation...
Page 734 32-Bit MCU RA0E1 Group R01UH1040EJ0110...

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