10.4 Clock Output Control Circuit Operations
The clock pulse is output as the following procedure.
<1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register
(CKS) (clock pulse output in disabled status).
<2> Set bit 4 (CLOE) of CKS to 1, and enable clock output.
Remark The clock output control circuit is designed not to output pulses with a small width during output enable/
disable switching of the clock output. As shown in Figure 10-4, be sure to start output from the low period
of the clock (marked with * in the figure). When stopping output, do so after securing high level of the
clock.
Figure 10-4. Remote Control Output Application Example
CLOE
Clock output
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CHAPTER 10 CLOCK OUTPUT CONTROL CIRCUITS
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Preliminary User's Manual U13420EJ2V0UM00
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