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(c) Repeat transmit mode
In this mode, data stored in the buffer RAM is transmitted repeatedly.
Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE10) of
the serial operating mode register 1 (CSIM1) is set to 1, and bit 7 (RE0) of the automatic data transmit/
receive control register (ADTC0) is set to 0.
Unlike the basic transmission mode, after the last byte (data in address FAC0H) has been transmitted,
the interrupt request flag (CSIIF1) is not set, the value at the time when the transmission was started is
set in the automatic data transmit/receive address pointer (ADTP0) again, and the buffer RAM contents
are transmitted again.
When a reception operation, busy control and strobe control are not performed, the P84/SI1, P81/BUSY,
and P80/STB pins can be used as ordinary input/output ports.
The repeat transmit mode operation timing is shown in Figure 14-13, and the operation flowchart in Figure
14-14.
Figure 14-13. Repeat Transmit Mode Operation Timing
SCK1
D7 D6 D5 D4 D3 D2 D1 D0
SO1
Caution
Since, in the repeat transmit mode, a read is performed on the buffer RAM after the
transmission of one byte, the interval is included in the period up to the next
transmission.
processing, the maximum interval is dependent upon the CPU operation and the value
of the automatic data transmit/receive interval specification register (ADTI0) (refer to
14.4.3 (6) Automatic data transmit/receive interval).
CHAPTER 14 SERIAL INTERFACE (SIO1)
Interval
D7 D6 D5 D4 D3 D2 D1 D0
As the buffer RAM read is performed at the same time as CPU
Preliminary User's Manual U13420EJ2V0UM00
Interval
D7 D6 D5
239
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