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Figure 7-5. Format of 8-Bit Timer Mode Control Register 5n (TMC5n)
Address: FF70H (TMC50) FF74H (TMC51)
Symbol
7
TMC5n
TCE5n
TCE5n
0
1
TMC5n6
0
1
TMC5n4
0
1
LVS5n
0
0
1
1
TMC5n1
0
1
TOE5n
0
1
Remarks 1. In PWM mode, PWM output will be inactive because of TCE5n = 0.
2. If LVS5n and LVR5n are read after data is set, 0 is read.
3. n = 0, 1
140
CHAPTER 7 8-BIT TIMER/EVENT COUNTER
After reset: 04H
6
5
TMC5n6
0
TMC5n4
TM5n count operation control
After cleaning to 0, count operation disabled (prescaler disabled)
Count operation start
TM5n operating mode selection
Clear and start mode by matching between TM5n and CR5n
PWM (Free-running) mode
Single mode/cascade connection mode selection
Single mode (use the lowest timer)
Cascade connection mode (connect to lower timer)
LVR5n
0
No change
1
Timer output F/F reset (0)
0
Timer output F/F set (1)
1
Setting prohibited
In other modes (TMC5n6 = 0)
Timer F/F control
Inversion operation disabled
Inversion operation enabled
Output disabled (Port mode)
Output enabled
Preliminary User's Manual U13420EJ2V0UM00
R/W
4
3
2
LVS5n
LVR5n
Timer output F/F status setting
In PWM mode (TMC5n6 = 1)
Active level selection
Active high
Active low
Timer output control
1
0
TMC5n1
TOE5n
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