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When using the busy control option, select the internal clock as the serial clock. Control with the busy
signal cannot be implemented with the external clock.
Figure 14-18 shows the operation timing when the busy control option is used.
Caution
The busy control cannot be used simultaneously with the interval time control function
of the automatic data transmit/receive interval specification register (ADTI0). If used,
the busy control is invalid.
Figure 14-18. Operation Timing When Busy Control Option Is Used (when BUSY00 = 0)
SCK1
SO1
D7
D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
BUSY
CSIIF1
TRF0
Caution
If the TRF0 is cleared, the SO1 pin becomes low level.
Remark CSIIF1: Interrupt request flag
TRF0: Bit 3 of automatic data transmit/receive control register (ADTC0)
When the busy signal becomes inactive, waiting is released. If the sampled busy signal is inactive,
transmission/reception of the next 8-bit data is started at the falling edge of the next clock.
Because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal
is sampled, even if made inactive by the slave. It takes 0.5 clock until data transfer is started after the
busy signal is sampled.
To accurately release waiting, the slave must keep the busy signal inactive at least for the duration of
1.5 clocks.
Figure 14-19 shows the timing of the busy signal and wait release. This figure shows an example where
the busy signal is active as soon as transmission/reception is started.
CHAPTER 14 SERIAL INTERFACE (SIO1)
Wait
Preliminary User's Manual U13420EJ2V0UM00
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Clears busy input
Busy input is valid
245
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