Operation List - NEC mPD780065 Series Preliminary User's Manual

22.2 Operation List

Instruction
Mnemonic
Group
8-bit data MOV r, #byte
transfer
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
XCH A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed.
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
314
CHAPTER 22 INSTRUCTION SET
Clock
Operands Byte
Note 1
2 4
3 6
3 –
Note 3
1 2
Note 3
1 2
2 4
2 4
2 –
2 –
3 8
3 8
3 –
2 –
2 –
1 4
1 4
1 4
1 4
2 8
2 8
1 6
1 6
1 6
1 6
Note 3
1 2
2 4
2 –
3 8
1 4
1 4
2 8
2 8
2 8
Preliminary User's Manual U13420EJ2V0UM00
Operation
Note 2
r ← byte
–
(saddr) ← byte
7
sfr ← byte
7
A ← r
–
r ← A
–
A ← (saddr)
5
(saddr) ← A
5
A ← sfr
5
sfr ← A
5
A ← (addr16)
9 + n
(addr16) ← A
9 + m
PSW ← byte
7
A ← PSW
5
PSW ← A
5
A ← (DE)
5 + n
(DE) ← A
5 + m
A ← (HL)
5 + n
(HL) ← A
5 + m
A ← (HL + byte)
9 + n
(HL + byte) ← A
9 + m
A ← (HL + B)
7 + n
(HL + B) ← A
7 + m
A ← (HL + C)
7 + n
(HL + C) ← A
7 + m
A ↔ r
–
A ↔ (saddr)
6
A ↔ (sfr)
6
A ↔ (addr16)
10 + n + m
A ↔ (DE)
6 + n + m
A ↔ (HL)
6 + n + m
A ↔ (HL + byte)
10 + n + m
A ↔ (HL + B)
10 + n + m
A ↔ (HL + C)
10 + n + m
) selected by the processor clock control
CPU
Flag
Z AC CY
× × ×
× × ×