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3.2 Processor Registers ............................................................................................................
3.2.1
Control registers .........................................................................................................................
3.2.2
General registers ........................................................................................................................
3.2.3
Special Function Register (SFR) ................................................................................................
3.3 Instruction Address Addressing ........................................................................................
3.3.1
Relative addressing ....................................................................................................................
3.3.2
Immediate addressing ................................................................................................................
3.3.3
Table indirect addressing ...........................................................................................................
3.3.4
Register addressing ...................................................................................................................
3.4 Operand Address Addressing ............................................................................................
3.4.1
Implied addressing .....................................................................................................................
3.4.2
Register addressing ...................................................................................................................
3.4.3
Direct addressing .......................................................................................................................
3.4.4
Short direct addressing ..............................................................................................................
3.4.5
Special-function register (SFR) addressing ...............................................................................
3.4.6
Register indirect addressing .......................................................................................................
3.4.7
Based addressing ......................................................................................................................
3.4.8
Based indexed addressing .........................................................................................................
3.4.9
Stack addressing ........................................................................................................................
CHAPTER 4 PORT FUNCTIONS .......................................................................................................
4.1 Port Functions ......................................................................................................................
4.2 Port Configuration ...............................................................................................................
4.2.1
Port 0 ..........................................................................................................................................
4.2.2
Port 2 ..........................................................................................................................................
4.2.3
Port 3 ..........................................................................................................................................
4.2.4
Port 4 ..........................................................................................................................................
4.2.5
Port 5 ..........................................................................................................................................
4.2.6
Port 6 ..........................................................................................................................................
4.2.7
Port 7 ..........................................................................................................................................
4.2.8
Port 8 ..........................................................................................................................................
4.2.9
Port 9 ..........................................................................................................................................
4.3 Port Function Control Registers ........................................................................................
4.4 Port Function Operations ....................................................................................................
4.4.1
Writing to input/output port .........................................................................................................
4.4.2
Reading from input/output port ...................................................................................................
4.4.3
Operations on input/output port ..................................................................................................
CHAPTER 5 CLOCK GENERATOR .................................................................................................
5.1 Clock Generator Functions .................................................................................................
5.2 Clock Generator Configuration ..........................................................................................
5.3 Clock Generator Control Register ......................................................................................
5.4 System Clock Oscillator ......................................................................................................
5.4.1
Main system clock oscillator .......................................................................................................
5.4.2
Subsystem clock oscillator .........................................................................................................
5.4.3
Scaler .........................................................................................................................................
5.4.4
When no subsystem clocks are used .........................................................................................
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