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1.7 Outline of Function
Item
Internal memory
ROM
High-speed RAM
Expansion RAM
Buffer RAM
Memory space
General register
Minimum instruction execution time
When main system
clock selected
When subsystem
clock selected
Instruction set
I/O port
A/D converter
Serial interface
Timer
Timer output
Clock output
Vectored interrupt
Maskable
Non-maskable
Software
Power supply voltage
Operating ambient temperature
Package
Note The capacity of internal flash memory can be changed by means of the memory size switching register (IMS).
32
CHAPTER 1 OUTLINE
Part Number
µ PD780065
40 Kbytes (Mask ROM)
1024 bytes
4096 bytes
32 bytes
64 Kbytes
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time changeable function
0.24 µ s/0.48 µ s/0.95 µ s/1.91 µ s/3.81 µ s (@ 8.38-MHz operation)
122 µ s (@ 32.768-kHz operation)
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
CMOS I/O: 60
• 8-bit resolution × 8 channels
• Low-voltage operation: AV
• 3-wire serial I/O mode:
• 3-wire serial I/O mode
(provided with automatic transmit/receive function): 1 channel
• 2-wire serial I/O mode:
• UART mode:
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter:
• Watch timer:
• Watchdog timer:
Three outputs: (8-bit PWM output enable: 2)
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(8.38 MHz with main system clock)
• 32.768 kHz (32.768 kHz with subsystem clock)
Internal: 14, External: 4
Internal: 1
1
V
= 2.7 to 5.5 V
DD
T
= –40 to +85°C
A
80-pin plastic QFP (14 × 14 mm)
Preliminary User's Manual U13420EJ2V0UM00
µ PD78F0066
Note
48 Kbytes
(Flash memory)
= 2.7 to 5.5 V
DD
1 channel
1 channel
1 channel
2 channels
1 channel
1 channel
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