NEC mPD780065 Series Preliminary User's Manual page 164

(1) Watchdog timer clock select register (WDCS)
This register sets overflow time of the watchdog timer and the interval timer.
WDCS is set by an 8-bit memory manipulation instruction.
RESET input sets WDCS to 00H.
Figure 9-2. Format of Watchdog Timer Clock Select Register (WDCS)
Address: FF42H After reset: 00H
Symbol 7
WDCS 0
WDCS2
0
0
0
0
1
1
1
1
Remarks 1. f : Main system clock oscillation frequency
X
2. Figures in parentheses are for operation with f
164
CHAPTER 9 WATCHDOG TIMER
R/W
6 5 4
0 0 0
WDCS1 WDCS0
12
0 0 2 /f
13
0 1 2 /f
14
1 0 2 /f
15
1 1 2 /f
16
0 0 2 /f
17
0 1 2 /f
18
1 0 2 /f
20
1 1 2 /f
Preliminary User's Manual U13420EJ2V0UM00
3 2
0 WDCS2
Overflow time of watchdog timer/interval timer
(489 µ s)
X
(978 µ s)
X
(1.96 ms)
X
(3.91 ms)
X
(7.82 ms)
X
(15.6 ms)
X
(31.3 ms)
X
(125 ms)
X
= 8.38 MHz
X
1 0
WDCS1 WDCS0