Interval Timer (16-Bit) Operations - NEC mPD780065 Series Preliminary User's Manual

7.4.5 Interval timer (16-bit) operations

When bit 4 (TMC514) of 8-bit timer mode control register 51 (TM51) is set to 1, the 16-bit resolution timer/counter
mode is entered.
The 8-bit timer/event counter operates as an interval timer which generates interrupt requests repeatedly at
intervals of the count value preset to the 8-bit compare registers (CR50, CR51).
[Setting]
<1> Set each register
TCL50:
CR50, CR51:
TMC50, TMC51: Select the clear & start mode by match of TM50 and CR50 (TM51 and CR51).
<2> When TMC51 is set to TCE51 = 1 and then, TCE50 is set to TCE50 = 1, count operation starts.
<3> When the values of TM50 and CR50 of cascade-connected timer match, INTTM50 of TM50 is generated.
(TM50 and TM51 are cleared to 00H)
<4> INTTM50 generates repeatedly at the same interval.
Cautions 1. Stop timer operation without fail before setting compare register (CR50, CR51).
2. INTTM51 of TM51 is generated when TM51 count value matches CR51, even if cascade
connection is used. Ensure to mask TM51 to prohibit interrupt.
3. Set TCE50 and TCE51 in a sequential order of TM51 and TM50.
4. Count restart/stop can only be controlled by setting TCE50 of TM50 to 1/0.
Figure 7-12 shows an example of 16-bit resolution cascade connection mode timing.
CHAPTER 7 8-BIT TIMER/EVENT COUNTER
Select count clock in TM50.
Cascade-connected TM51 need not be selected.
Compared value (each value can be set at 00H through FFH)
TM50 → TMC50 = 0000×××0B ×: don't care
TM51 → TMC51 = 0001×××0B ×: don't care
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