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(d) Bit shift detection by busy signal
During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur
because noise is superimposed on the serial clock signal output by the master device. Unless the strobe
control option is used at this time, the bit shift affects transmission of the next byte. In this case, the master
can detect the bit shift by checking the busy signal during transmission by using the busy control option.
A bit shift is detected by using the busy signal as follows.
The slave outputs the busy signal after the rising edge of the eighth serial clock during data transmission/
reception (in order not to keep transmission/reception waiting by the busy signal at this time, make the
busy signal inactive within 2 clocks).
The master samples the busy signal in synchronization of the falling of the leading side of the serial clock.
If a bit shift does not occur, all the eight serial clocks that have been sampled are inactive. If the sampled
serial clocks are active, it is assumed that a bit shift has occurred, and error processing is executed (by
setting bit 4 (ERR0) of the automatic transmit/receive control register (ADTC0) to 1).
Figure 14-22 shows the operation timing of the bit shift detection function by the busy signal.
Figure 14-22. Operation Timing of Bit Shift Detection Function by Busy Signal (when BUSY00 = 1)
SCK1
(master)
SCK1
(slave)
SO1
D7
D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
BUSY
CSIIF1
CSIE10
ERR0
CSIIF1: Interrupt request flag
CSIE10: Bit 7 of serial operating mode register 1 (CSIM1)
ERR0:
Bit 4 of automatic data transmit/receive control register (ADTC0)
CHAPTER 14 SERIAL INTERFACE (SIO1)
D7
D7 D6 D5 D4 D3 D2 D1
D7
D7 D6 D5 D4 D3 D2 D1
Busy not detected
Preliminary User's Manual U13420EJ2V0UM00
Bit shift due to noise
D0
D0
Error interrupt request
generated
Error detected
249
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