16-Bit Timer/Event Counter Operations; Interval Timer Operations - NEC mPD780065 Series Preliminary User's Manual

6.5 16-Bit Timer/Event Counter Operations

6.5.1 Interval timer operations

Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in
Figure 6-7 allows operation as an interval timer. Interrupt request is generated repeatedly using the count value set
in 16-bit timer capture/compare register 00 (CR00) beforehand as the interval.
When the count value of 16-bit timer/counter 0 (TM0) matches the value set to CR00, counting continues with the
TM0 value cleared to 0 and the interrupt request signal (INTTM00) is generated.
Count clock of the 16-bit timer/event counter can be selected with bits 0 to 1 (PRM00, PRM01) of prescaler mode
register 0 (PRM0).
See 6.6 16-Bit Timer/Event Counter Operating Precautions (2) 16-bit Compare-Register Setting about the
operation when the compare register value is changed during timer count operation.
Figure 6-7. Control Register Settings for Interval Timer Operation
TMC0 0 0 0
CRC0 0 0 0
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See Figures
6-2 and 6-3.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
0 1 1 0/1 0
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
0 0 0/1 0/1 0
Preliminary User's Manual U13420EJ2V0UM00
Clears and starts on coincidence between TM0 and CR00.
CR00 as compare register