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Instruction
Mnemonic
Group
16-bit
ADDW
AX, #word
operation
SUBW
AX, #word
CMPW
AX, #word
Multiply/
MULU
X
divide
DIVUW
C
Increment/
INC
r
decrement
saddr
DEC
r
saddr
INCW
rp
DECW
rp
Rotate
ROR
A, 1
ROL
A, 1
RORC
A, 1
ROLC
A, 1
ROR4
[HL]
ROL4
[HL]
BCD
ADJBA
adjust
ADJBS
Bit
MOV1
CY, saddr.bit
manipulate
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
318
CHAPTER 22 INSTRUCTION SET
Clock
Operands
Byte
Note 1
3
6
3
6
3
6
2
16
2
25
1
2
2
4
1
2
2
4
1
4
1
4
1
2
1
2
1
2
1
2
2
10
2
10
2
4
2
4
3
6
3
–
2
4
3
–
2
6
3
6
3
–
2
4
3
–
2
6
Preliminary User's Manual U13420EJ2V0UM00
Operation
Note 2
AX, CY ← AX + word
–
AX, CY ← AX – word
–
–
AX – word
AX ← A × X
–
AX (Quotient), C (Remainder) ← AX ÷ C
–
r ← r + 1
–
(saddr) ← (saddr) + 1
6
r ← r – 1
–
(saddr) ← (saddr) – 1
6
rp ← rp + 1
–
rp ← rp – 1
–
← A
–
(CY, A
, A
7
0
m – 1
← A
–
(CY, A
, A
0
7
m + 1
(CY ← A
← CY, A
–
, A
0
7
(CY ← A
← CY, A
–
, A
7
0
← (HL)
A
, (HL)
12 + n + m
3 – 0
3 – 0
← (HL)
(HL)
3 – 0
7 – 4
← (HL)
12 + n + m
A
, (HL)
3 – 0
7 – 4
← (HL)
(HL)
7 – 4
3 – 0
–
Decimal Adjust Accumulator after
Addition
–
Decimal Adjust Accumulator after
Subtract
CY ← (saddr.bit)
7
CY ← sfr.bit
7
CY ← A.bit
–
CY ← PSW.bit
7
CY ← (HL).bit
7 + n
(saddr.bit) ← CY
8
sfr.bit ← CY
8
A.bit ← CY
–
PSW.bit ← CY
8
(HL).bit ← CY
8 + n + m
) selected by the processor clock control
CPU
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
← A
) × 1 time
m
← A
) × 1 time
m
← A
) × 1 time
m – 1
m
← A
) × 1 time
m + 1
m
← A
,
7 – 4
3 – 0
← A
,
3 – 0
3 – 0
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
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