Standby Function Operations; Halt Mode - NEC mPD780065 Series Preliminary User's Manual

19.2 Standby Function Operations

19.2.1 HALT mode

(1) HALT mode setting and operating statuses
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock.
The operating statuses in the HALT mode are described below.
HALT Mode
Setting
Without Subsystem
Item Clock
Clock generator Both main system clock and subsystem clock can be oscillated. Clock supply to CPU stops.
CPU Operation stops.
Port (Output latch) Status before HALT mode setting is held.
16-bit timer/event Operable
counter
8-bit timer/event Operable
counter
Watch timer Operable when f
selected as count clock
Watchdog timer Operable
A/D converter Stop
Serial interface Operable
External interrupt Operable
Bus line AD0 to AD7 High impedance
during
A8 to A15 Status before HALT mode setting is held.
external
ASTB Low level
expansion
WR, RD High level
WAIT High impedance
Notes 1. Including case when external clock is not supplied.
2. Including case when external clock is supplied.
CHAPTER 19 STANDBY FUNCTION
Table 19-1. HALT Mode Operating Statuses
During HALT Instruction Execution
Using Main System Clock
With Subsystem
Note 1 Note 2
Clock
7
/2 is Operable
X
Preliminary User's Manual U13420EJ2V0UM00
During HALT Instruction Execution
Using Subsystem Clock
With Main System With Main System
Clock Oscillation Clock Oscillation Stopped
Operable when TI00
is selected.
Operable when TI50,
TI51 are selected as
count clock.
Operable when f
selected as count clock.
Operation stops.
Operable during
external SCK.
is
XT
295