NEC mPD780065 Series Preliminary User's Manual page 250

(5) Timing of interrupt request signal generation
The interrupt request signal is generated in synchronization with the timing shown in Table 14-2.
Table 14-2. Timing of Interrupt Request Signal Generation
Single mode
Repetitive transmit mode
If bit shift occurs during transmission/reception
(6) Interval time of automatic transmission/reception
Because read/write to/from the buffer RAM using the automatic transmit/receive function is performed
asynchronously with CPU processing, the interval time is dependent on the CPU processing of the timing of
the eighth rising of the serial clock and the set value of the automatic data transmit/receive interval specification
register (ADTI0). Whether the interval time is dependent on ADTI0 is selected by setting of the bit 7 (ADTI07)
of ADTI0. If ADTI07 is reset to 0, the interval time is 2/f
by the set contents of ADTI0 or interval time (2/f
is greater.
Figure 14-23 shows the interval time of automatic transmission/reception
Remark f : Serial clock frequency
SCK
Figure 14-23. Interval Time of Automatic Transmission/Reception
SCK1
SO1 D7 D6 D5 D4 D3 D2 D1 D0
SI1 D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1
The following expression must be satisfied to access the buffer RAM.
1 transfer cycle + interval time
In the case of a "high-speed CPU & low-speed SCK
a "low-speed CPU & high-speed SCK
In this case, make sure that a sufficient interval time elapses by using the automatic data transmit/receive
interval specification register (ADTI0), so that the above expression is satisfied.
Note The speeds of the CPU clock and SCK differ depending on the type of CPU core.
250
CHAPTER 14 SERIAL INTERFACE (SIO1)
Operating Mode
Master mode
Slave mode
Interval
≥
Read access + Write access + CPU buffer RAM access (time)
Note
", the interval time is necessary.
Preliminary User's Manual U13420EJ2V0UM00
Timing of Interrupt Request Signal
10th serial clock at end of transfer
8th serial clock at end of transfer
Not generated
8th serial clock
. If ADTI07 is set to 1, the interval time determined
SCK
) according to CPU processing is selected, whichever is
SCK
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Note
", the interval time is not necessary. In the case of