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Input Capacitance: 0.2 pF and then, through 500 Ω, 3 pF.
Probes
Minimum Input Overdrive: 250 mV or 30% of input (whichever is
greater) above the pod threshold.
Threshold Range Increments: ±5.0 V in 10 mV increments.
Threshold Setting: Preset TTL, ECL, or User-defined on a per pod
basis.
Input Dynamic Range: ±5 V about the threshold.
Maximum Input Voltage: 40 V peak-to-peak, CAT 1.
Synchronous State
Analysis
Maximum External Clock Speed: 1 GHz, requires a periodic clock.
Minimum State Speed: 20 MGSa/s, requires a periodic clock.
Minimum Detectable Pulse Width: 900 ps.
Channel Count: 16 per card, up to 80 in one frame.
Channel-to-Channel Skew across up to 80 channels:
Per pod
Across pods
Memory Depth per Channel: 65536 samples.
State Clocks: One external clock is available on the master board. No
clocks are available on the expander board. Clock edge is selectable as
positive or negative.
State Clock Duty Cycle Range:
1 GHz through 500 MHz
500 MHz through 250 MHz 30% - 70%, typical.
250 MHz through 20 MHz
Oversampling: 2x, 4x, 8x, 16x, and 32x, with a maximum rate
of 2 GSa/s.
250 ps, typical.
1 ns, typical.
250 ps, with manual deskew.
45% - 55%, typical.
20% - 80%, typical.
Specifications and Characteristics
Characteristics
12–5
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