Spi Interface - Tektronix RTX100A Service Manual

Table 1-2: Mainframe (Cont.)
Characteristics
PLL
Frequency
Output clock
Output rate
TS clock
(Internal and external
reference, 27 MHz and 10 MHz)
(External parallel clock)
(External serial clock)
P/N and Jitter (serial clock)

SPI interface

Connector type
Data rate
Pin assignments
Output
Output level, typical
Offset
Output resistance, typical
RTX100A ISDB-T RF Signal Generator Service Manual
Description
50 MHz to 100 MHz, locked to reference clock
50 MHz maximum (serial clock)
26.75 MHz maximum (parallel clock)
214 Mbps maximum
64 Kbps minimum
TS clock = (X / (2 * Y * Z) ) * 27 MHz
15362 < X < 31248
1686 < Y < 3376
2 ≤ Z ≤ 65536
TS clock = (X / (2 * Y * Z) ) * external parallel clock, 214 MHz maximum
15632 < X < 31248
1 < Y < 16383
2 ≤ Z ≤ 65536
TS clock = (X / (2 * Y * Z) ) * external serial clock / 8,32 MHz maximum
15632 < X < 31248
1 < Y < 16383
2 ≤ Z ≤ 65536
< - - 104 dBc/Hz at 21.455707 MHz +20 kHz (RBW=300 Hz)
D-sub, 25 pin
256 Kbps to 214 Mbps
1 DCLK
2 GND
3 to 10 DATA 7 to DATA 0
11 DVALID
12 PSYNC
13 Shield
14 DCLK
15 GND
16 to 23 DATA 7 to DATA 0
24 DVALID
25 PSYNC
330 mV to 550 mV (termination: internal 100 Ω, external 100 Ω), bus LVDS with 50 Ω
termination
1.1 V to 1.5 V
100 Ω, between differential outputs (output off)
Specifications
1-5