Serial Interfaces - Tektronix RTX100A Service Manual

Specifications
DATA 0- - 7
DCLK
PSYNC
DVALID
DATA 0- - 7
DCLK*
DATA 0- - 7
DCLK*
Figure 1-1: Timing diagram of the SPI and universal parallel/serial interfaces
1-10
188 bytes
5 ns 5 ns
Output data delay
Th = T/2  T/10: SPI and universal parallel interfaces
Th
Th = T/5 T/10: universal serial interface
Input data hold time
Transition period
* In the universal parallel/serial interface,
the polarity of DCLK can be inverted.
RTX100A ISDB-T RF Signal Generator Service Manual
T (f/1)
T/2  T/10
Input clock pulse width