Sony CXD2701Q Data Book page 91

SONY
Pin
Description
Pin
No.
Symbol
I
I/O
'
Description
1
DVdo
Digital
power
supply
2
TEST
Test
pin.
Fixed
at
"Low*
in
normal
use.
3
4
IN
IT
Signal
that
activates
resynchronization
at rise
LRCK LRCK
input
(8fs)
5
DATAR
Right
channel data
input
(Sfs):
16
to 18-bit
data, LSB-flrst
6
DATAL
Left
channel data
input
(Sfs);
16
to
1
8-bit data, tSB-first
7
BCK
BCK
input
8
DVss
Digital
GND
9
512fs
512fs Clock
output
10
XVss
Clock
GND
11
XIN
1
Crystal
oscillator
input (512fs)
12
XOUT
Crystal oscillator
output (512fs)
13
XVdd Clock
power
supply
14
Vsub Connected
to
substrate
GND
15
AVddR
Analog power
supply
for right
channel
16 R1
(+)
o
Right-channel
PLM
output (in-phase)
17
AVssR
Analog
GND
for right
channel
18 R1(-) Right-channel
PLM
output (opposite
phase)
19
R2(
+
)
Right-channel
PLM
output (in-phase)
20
R2(-) Right-channel
PLM
output (opposite
phase)
21
AVdd Analog power supply
22
AVss Analog
GND
23
L2(-) Left-channel
PLM
output (opposite
phase)
24
Law
Left-channel
PLM
output (in-phase)
25
LK-)
Left-channel
PLM
output (opposite
phase)
26
AVssL Analog
GND
for
left
channel
27
L1W
Left-channel
PLM
output (in-phase)
28
AVddL
—
Analog power
supply
for
left
channel
I
-87
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