Sony CXD2701Q Data Book page 137

SONY,
CXD1160AP;AQ
(1)
32bit
delay
mode
8y
turning
DIO,
of
the
microcomputer
interface
R mode
to
'H\ 32bit delay
mode
is
set
on.
To
realize this,
the following
hardware conditions
should be
met.
LRCK2136KCK=272ACK
With
32bit
delay
mode,
delay for
all
32bif
Dl/DO
registers
is
possible.
DIH
En
F...
D
I
L
L
I
S
E,.
E,
E,
Cao
"Bit
DOH
P.. Fa*
-F,t t„
DOL
ttt
Fm--
F,
F,
Timing
(LRCK=136KCK
Example)
134135
31
32
33
34
65 66 67 6S
93
100
101
102
133134135
kck
ruw
nnnsu rmjuu
juuuu
njuiRr
ksl
n n
—
xras
J~~|_
_TT
X
CAS
XWSO(WE)
U
JOT
S
u
xu
—
u ru
u
nr
v
i
i
A7-A5
EOC
3XDC
DEDC
ZKZEDC
DEDC
A4-ao
WOIB
IGDKOIK
XHKOB
XEKJOSt JdUKOE*
do
o a
n
a a
di
oo
oo
i
t
-Calculating operations-
I
Should
the
data
written
last
between
cycle to
66
in
DO
register
be
at
CHl(n), data
CHl(n-r) from the previous cycie
134 up
to the
present cycle
65
in
Ol
register
can
perform
read.
Similarly,
should data
written last
between
cycle
68
and
last
cycle
1
in
DO
register
be
at
CH2(n), data CH2(n-r)
between cycle
66
to
133
in
DI register
can perform
read.
- 133-