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SONY
CX0
-
3S5AC
Microcomputer
Interface
Suppose
that
the
microprocessor
sends
input to
the pins
shown
in
the
figure
below.
The CXD13S5AQ's
internal
DSP
program,
IIR
filter
coefficient,
MIX
coefficient
and
attenuation
values
can be
re-written
partially
or
totally
depending on which
of
the various operating
modes
is
selected.
•
PRGDT
24-bit length
serial
data
transferred
in
one
cycle
•
PRGCK
The
serial
clock.
When
triggered
by
the
rising
edge
of
this
signal,
the
serial
data
is
transferred
to
the
internal
shift
register.
•
pRQL
The
entire
contents
of
the
24-bit length
serial
data
in
the
shift
register
is
latched
by
the gate
pass
[active
low
level).
At
the
same
time,
the
rising
edge
of
this
signal
initiates
an
interna]
request
for
processing.
•
DSP
When
set
V.
the
DSP
program and
K-RAM
data
transfer (unction
is
disabled.
MIX
coefficient
is
fixed at
m0=1, m1=0.
This
transfer
format (next
item) timing
are
shown
in
the
figure
below.
PRGCK
~
z
j
,
5
s
J
t
9
10
i
ID
l«
a
l«
IT
l»
»
ZO
1>
«
2)
M
S
(1 -bit)
:
When
set
"L",
transfers
DSP
information;
when
*H".
transfers
non-DSP
information.
L
(7-bit)
:
Identification
label
for
transfer
data or
transfer
address
information.
D
(16-bit)
:
Transfer
data; not
used
in
MODE
transfer
operations.
L
and
D
are
in
LSB
first
format
PRGD
is
triggered
by
the
rising
edge
signal of
PRGCK.
The
falling
edge
of
PRGL
latches the
internal register.
Description
of
Modes
1)
DATA
RAM
address
External
ORAM'S
relative
address
2)
DSP
coefficient instructions
DSP
program and
coefficient
The
multiplication coefficient
K
(8-bit)
ot
the
DSP
portion
Is
equal
to
7FH
^
X1,
80H
x
(-1)-
I
167-
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