Sony CXD2701Q Data Book page 45

SONY
CXD2554M.P
Pin Description
Pin No.
Symbol WO
Description
CXD2554P CXD2554M
1
1
TEST
I
Test
pin.
Fixed
at
'L'
level
in
normal operation
mode.
2
2
8fs /4fe
I
To
specify
FIR
3.
FT:
8fe
V.
4fs
3 3
XOUT
Master clock output
(f
-
384fs)
4
4
XIN
I
Mastef clock
input
(f
= 384fs)
5
6
Vdd
-
Power
supply (+5
V)
6
9 BCK
1
BCK
input
7 10
DATA
1
Serial
data
input
(2's
complement)
8
11
LHCK
1
LRCK
input
9
12
'NIT
1
Re- synchronized by
rising
edge
of this signal
10
13
LATCH
1
Latcti
clock input
11
14 SHIFT
1
Shift
clock input
12 15
ATT
1
Attenuate data
input
13
16
BCKO
o
BCK
output
14 19
Vss
(GND)
-
Powet supply
(C
v)
15 21
DATAR
4fs
mode:
WCK
output
8fs
mode:
RCH
serial
data output
(2's
complement)
16
22
DATAL
4fs
mode:
LCH
and
RCH
time
division serial
data
output
(2
!
s
complement)
8fs
mode:
LCH
serial
data output
(2's
complement)
17 23
LRCKO LRCK
output
18
24
SLOT
1
To
specify output
slot.
*H': 18-bit slot
V:
16-bit
slot
-
5, 7, 8,
17,
18,
20
<NC)
-
No
connection
I
*
TEST,
8fs
/4fs
and
SLOT
pins:
Pull
down
resistance
-4] -