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SONY
cxd2to;q
Cautions
when
using
DRAMs
DRAM
Address
The
DRAM
address
generation section
has a
16-bit
binary
counter incremented during
2/fs
[program
cycles).
Absolute address
(bis to bo)
are generated.
The
DRAM
addresses
(ais to
ao).
assume
the value calculated by
adding
the absolute
addresses
(bts to be)
and
the
DSP
programming
relative
addresses
(m
to
re).
(ais to ao)
=
(bis to bo)
+
(rw
to
ro)
Carry-over
is
ignored.
In
the
case
of
256K DRAMs.
in
order
for
the
upper 2
bits
(ais
and an)
not
to
be used
among
relative
addressing,
addresses
ris
and
ri4
are
made
invalid.
<IM
D-RAM>
^""--•-^Pin
Name
Add
^"~^\^
A8
A7
A6
AS
A4
A3
A2
A1
AO
Row
R
ae
a7
ae
as
34
as
32
ai
ao
Column
Co
ais
an
at
a
air
an
aio
at
Cj
1
Cz
1
C3
1
1
<256K
D-RAM>
^""-.^Fln
Name
Add
^""""'-v^
A3
A7
A6
A5
A4
A3
A2
A1
AO
Row
R
m
ao
as
a*
aj
32
31
ao
Co
ais
aiz
an
aio
as
ae
Column
Ci
1
C
2
1
Cj
1
1
RAS
L
CAS
n
Add
^dz^ozxzxia:
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page
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