Sony CXD2701Q Data Book page 157

SONVb
CXD1
1
60AP/aq
Example
2)
fKCK=6.144
MHz
fs=44.1
KHz
N
f
Ni
=139
(Cycle
to
cycle 138)
1
Ni+1
=140
(Cycle
to
cycle 139}
Serial I/O input register
n=
!ti,-4£n
SfM
.
(135
^n
£139}
I
Cycle
to
cycle
134 usable
-
{
Cycle
135
to
cycle
139 unusable
I
1
3
1
Serial I/O
output register
24
clock
system
K-4—
*
—
(139,3...
)<n < ti-2—
I
—039.3...)
N1.3...
<ti
<
S-0. I...
v>
*'-l,0
1
=
111,-1, II,.
!
= (138.139.0.'
f
Cycle
1
to
cycle
137
usable
"
|
Cycle
137, 139, cycle
unusable
II
3
1
Serial I/O
output register
32 clock systerr
N-4—
t
—
(139.3..
.)<n < Ji-2—
«
—-(139.3...)
fi-2.0...
<n <
N-0.5.
..
K-2SII
SN-1
11=
ffi-2.
S-l'
=
iS
I
-2.S,-l,S
i
:
=
137. 138. 139J
/Cycle
to
cycle
136 usable
"(Cycle
137
to
cycle
139 unusable
Delay
I/O (Serial
mode) and
register
(1)
Delay
I/O input register
Delay
I/O input register
is
input twice during
1
sampling period.
For
one
of
those
2
instances the timing
is
the
same
as
for serial I/O.
For the other instance the conditions for
the transfer with this register
as source
or the cycle n
when
MPY
cannot be
executed
are:
1
fKCK
1
I
fKCK
3
4
—
<n
<
2-
M
2 fS
4 2
fS 4
as
n=
—
ckck;
2
1
H«
1 *
fKCK
1
2
fS
4
"
2 fS
4
1
fKCK
,
1
.
accordingly n
a
=
i«iaxn:n<—
~- -4—
I
I
Cycle
to
cycle n2
data
transferred during
LRCK
L level
of
the
previous
sampling
level
is in
the
register
and can
be handled
freely.
Cycle
(rte+1),
cycle (Ns+2)
Usage
prohibit
cycle
Cycle
(na+3) to
cycle
(Ni-5)
data
transferred during
LRCK H
level of
the
present sampling period
is in
the register
and can
be handled
freely
Cycle
(N--4) to 'cycle
(Ni-1)
Usage
prohibit
cycle
*ln certain
cases
cycle (nz+3) also
becomes
usage
prohibit cycle.
Please check
when
necessary
-
153-