Sony CXD2701Q Data Book page 211

SONY
CXD1211P
Pin Configuration
(Top View) and
Description
28 27 26 25 24 23
22
21
20
19 18
17
16 15
nnnnnnnnnnnnnn
O
"U
U
U
U
U U U U
LTD'
U
LI
U
U
1
2
3 A
5 6 7 6 9 10
11
12 13 14
No. Symbol
I/O
Description
1
BCK
Bit
clock
input.
Data
is
taken
in
at rising
edge.
2
DATA
Digital
audio data input
1
INRZI.
3
DATS
Digital
audio data
Input 2 INRZ).
4
LRCK
LR
clock
input.
"H":
L
channel "L": R channel
5
VRDTY
Validity flag input.
"H"
is
input
when
data
is
processed
for interpolation, etc.
6
|
CKS1
Frequency
selection input
1
for
clock to
EXTAL.
1
92Fs, 384Fs/128Fs,
256Fs
7 Vss
-
GND
8
CKS2
Frequency
selection input
2
for
clock to
EXTAL.
256Fs, 384Fs/128Fs,
192Fs
9
V1SBF
MSB
first
rLSB
first
selection input for
DATA
and
DATB.
10
C8
Preset input of
channel
status
data
bit
8.
11
eg
Preset input of
channel
status
data
bit
9.
12
CIO
Preset input of
channel status data
bit
10.
13
MUTE
Muting
input.
"H":
Only the audio
data on
TX
will
be
0.
14
EXTAL
Clock
input.
The
frequency
is
selected
from 128Fs/192Fs/256Fs,'384Fs
at
CKS1
(pin
61
and
CKS2
(pin 81.
15
TX
Output
of transmitting
data converted
in
digital
audio
interface format.
16
ABSL
Selection input
of
DATA
(pin
21/DATB
(pin 3)
and
C2
[pin
22},'C2B
(pin
19)
17
TEST
Test
mode
set input.
Fixed
to
"L"
in
normal
use.
'8
XRST
Reset
input.
Fixed to
"H"
during operation.
19
C2B
Preset input 2
of
Channel
Status
Data
bit
2.
20
C3
Preset input
of
Channel
Status Data
bit
3.
21
Vdd
-
+ 5V
22
C2A
Preset input
1
of
Channel
Status
Data
bit 2.
23 C1
Preset input of
Channel
Status
Data
bit 1.
24
C29
Preset
input of
Channel Status Data
bit
29.
26
C2B
Preset input of
Channel Status Data
bit
28.
26
C25
Preset
input of
Channel
Status Data
bit
25.
27
C24
Preset input
of
Channel
Status Data
bit
24.
28 UBIT
User
Data
input.
I
-207-