Sony CXD2701Q Data Book page 159

S
O
NYj
CXD1
1
60
AP/AQ
33
1
"¥%
^
Delay
I/O output register
32
clock
system
—
—
123-4- <n
<—
128-2—
—
64
4 64
4
3
1
81—
<tl
<63—
ii-
{62,631
4
4
I
Cycle
to cycle 61
usable
Cycle 62
to
cycle
63 unusable
Cycle 64
to
cycle
125
usable
Cycle 126
to
cycle
127
unusable
Example
2)
fKCK=6,144
MHz
fe-44.1
KHz
N
_
Ni
=139
(Cycle
to
cycle 138)
Ni
+
1
=140
(Cycle
to
cycle 139)
Delay
I/O input register n
"
<_
^- 139.3 ...-4
—
=
65.4...
.-.n=65
'
Cycle
to
cycle
65 usable
Cycle 66
to
cycle 67
unusable
Cycle 68
to
cycle
134 usable
Cycle
135
to
cycle
139 usable
25
I
25
3
Delay
I/O output register
24
clock
system
—
139. 3...
-4
—
<n
<—
-139.
3.
..
-a—
68.3...
<n <
69.
8.
.
.
.
n=69
Cycle
1
to
cycle
68 usable
Cycle 69
unusable
Cycle 70
to
cycle
137
usable
Cycle 138
to
cycle
unusable
33
33
3
Delay I/O
output register
32
clock
system
-^-
139.3... -4
—
<n
<—
139, 3...
-2—
67.5...
<n <
69.
0.
.
.
n=
i'B8,
69}
[Cycle
to
cycle
67
usable
I
Cycle
68
to
cycle
69
unusable
I
Cycle 70
to
cycle
136 usable
^Cycle 137
to
cycle
139
unusable
I
155