Sony CXD2701Q Data Book page 75

Semiconductor ic, digital audio ics
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SONY
CXD2557M
3,
MUTE
Output
When
Silence
Is
Detected
If
data judged
as
"silence"
Is
input
continuously
for
1
6,382
cycles
(1
6,382
fs
cycles
of
LRCK),
the
mute
signal
is
output
("L" level)
on
the
rising
edge
of
the
second subsequent
LRCK
cycle.
1"*
/"
"\
1
16382nd
16.382nd
sifence
data
L
silence
data
R
\
/
V_
MUI-L.
H
"A
The
mute
signal
is
reset
as
shown
in
the
diagram
below,
tf,
for
example, sound data
is
detected
in
the
Lch
signal,
the
internal
TRST
L
signal
goes
to
"L"
on
the
rising
edge
of
the
fourth
BCK
cycle following the
falling
edge
of
LRCK. and
the
internal
counter loads the
initial
value.
As a
result,
the
MUTE
signal
is
reset
on
the
rising
edge
on
the next
LRCK;
the
same
occurs
with-
the
Rch
signal.
Note) The
TRST
L
and
R
signals
are
flags
showing whether
the
input
data
is
silence or
sound.
Silence:
"H";
sound:
"L".
LRCK
_/
\
/
Silence
data
Silence
data
Sound
L
R
L
~^\
r
data
Sound
dais
Sili
R
\
nee
data
S
L
ence
R
/
\
data
Silence
data
Silence dat
L
R
TRST
L
v
/
MUT-L
/
TRST
R
\
r~
MUT-R
_/
I
4.
Forcing
a
MUTE
Output Using
the
DMUT
Input
When
"H"
is
input
to
the
DMUT
pin,
a
MUTE
signal
Is
forcefully
output to both
L
and
R
channels
on
the
rising
edge
of
the next
LRCK. The
MUTE
signal
is
reset
in
the
same
manner.
1)
When
DMUT
is
turned
ON
while
sound
data
is
continuing:
LRCK
J
\
/
\
I
\_
DMUT
//////////////////////////////////////////////////M
~\
MUT-U R
\
r~
2)
When
DMUT
is
turned
OFF
while
sound
data
is
continuing:
LRCK
J
\
-J
\
/
V-
DMUT
MUTL.
R
-71 -

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