Sony CXD2701Q Data Book page 119

SONY,
CXD1
1
60AP/AQ
Internal
RAM
structure
123-
10
I
-RAM
24bi64w
l-RAM
Instruction
RAM
((-RAM) integrated
in
CXD1160AP/AQ
is
composed
o(
address
to
63 (24b#64w)
with
a
command
word
length of 24bit.
Commands
are transferred
one
(24bit)
at
a
time through the
microcomputer
interface
mode
1,
from
the exterior.
Each
transfer
can
be
sent to
the desired
address.
External interrupt
is
executed
at serial
I/O
LRCK
and
BCK. Every
sampling cycle
a
jump
is
forcibly
made
to
address.
That
Is,
at
every sampling
the
command
is
repeatedly
executed from
address.
For executive
commands
there are,
forced
jump
(JMP). condition
jump,
sub
routine call
(CAL),
sub
routine turn
(RTN) and loop
jump
(LP
J).
They
all fly
to
the
absolute address.
There are 2 stack
stages
and
usage
in
conjunction with
double sub routine or
loop
jump
is
possible.
Loop
counter
is
conposed
of 4bit
and
loop
jump can be
executed up
to
15 times.
Command
execution cycle
is
given according
to
MPY
mode
in
1/2/3/
cycle time.
The number
of
cycles that
can be executed
within
1
sampling
section
depends
on the
sampling frequency
(fs)
and the cycle clock (fKCK=fiCK). Let's
assume
that at
sampling
section
1
we
have L
cycle (cycle to
cycle
L-1).
Here, the
last
cycle (L-1)
called
KSH
cycle
cannot be
executed
because
of
the
command
or
coefficient transfer
section
of
the
microcomputer interface.
Cycle
(L-2)
called
KSL
cycle
can be executed
with
the exception
of
K-RAM
handling.
Example
1)
fs*ttWi
r*,.»+f«i»-+f«M=«.l*«B^
a
4» x
^3
In
this
case
fKC*/fs=128.
There are
128 cycles (cycle
to
127).
Cycle
to
cycle
125
Execution cycle
Cycle
126
Execution possible
with the
exception
of
K-RAM
handling.
Cycle
127
Execution impossible
Example
2)
fs=44.Ui
r. ch
=6.14411
In
this
case
at
taCK/fe- 139.3...
both
139 cycle (cycle to
cycle 138)
and 140
cycle (cycle to
cycle 139)
exist.
Cycle
to
cycle
136
Execution cycle
Cycle
137
Execution passible with the
exception
of
K-RAM
handling
Cycle
138,
139
Execution
impossible.
The sequencial execution
address
of
63 address
is
address.
When
Power
is
ON
the contents of
l-RAM
are not determined.
I
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