Sony CXD2701Q Data Book page 122

SONY,
CXD1160AP.'AG
Interface
Clock
circuit
There
are 2
methods
to
generate
the
master clock
ACK
in this IC.
(1)
The
clock input
from
MCK1
input pin
is
frequency divided
by 2
internally to
be read/
for
use.
(2)
The
clock input
from
MCK2
input pin
is
directly
used.
|MCK2>—
2U=O-0
AC
K
+5V
MCK
1
MCK
2
(1)
When
the input
is
from
input pin
MCK1
Fix input pin
MCK2
to
+5V
fwc*«" 2f ACK
(2)
When
the input
is
from
input pin
MCK2
Fix input pin
MCK1
to
+SV
or
to
GND
In
any case
the
maximum
frequency
of
master clock
ACK
is
f,.,-.;S15.36MKz(=<18Kx32M
Moreover as
this
IC
makes
use
of
a
dynamic
F/F internally,
it
is
not possible
to stop the the
master
clock
and keep
the
internal
condition
as
it
is.
Cycle
clock
ICK
(or
KCK)
inside the IC
is
twice
ACK
master
clock.
Commands
differ
according
to
type.
There are
1
cycle/2 cycle
and
3 cycle
commands.
+5V
[_
MCK1
MCK2
& MCK
1
MCK2
-
118