Sony CXD2701Q Data Book page 165

SONY
CXD1355AQ
Pin
No,
Symbol
I/O
Description
16
XIN
O
Liquid crystal display oscillation circuit
input, fxt
=
384fs.
17
VddI
Power
supply (+5 V)
18 18/16
!
Input for
selecting
output data
bit-length. "H": 18-bit;
"L":
1
6-bit.
19
I/01 I/O
External
DRAM
data
1/01
.
20
I/02 I/O
External
DRAM
data
I/02.
21
CAS
External
DRAM
column address strobe output.
22
I/G3
I/O
External
DRAM
data
1/03.
23 I/04 I/O
External
DRAM
data I/04.
24
WE
External
DRAM
write-enable output. Active
when
set
"L".
25
A0
External
DRAM
address output AO.
26
RAS
External
DRAM
low-address strobe output.
27
A1 External
DRAM
address output A1.
28
Vss2
GND
29
A2
o
External
DRAM
address output A2.
30
A3
External
DRAM
address output A3.
31
A4
External
DRAM
address output A4.
32
A5
External
DRAM
address
output A5.
33
A6
Externa!
DRAM
address
output A6.
34
A7
External
DRAM
address output A7.
35
A8
External
DRAM
address output AS.
36
TEST
I
Test
pin.
Fixed
at
GND
in
normal operation
mode.
37
OFST
I
Offset select
input. "H": offset; "L":
non-offset.
38
DPOL
I
Input
data
for
inverted/non-inverted select. "H":
inverted;
"L":
non-inverted.
39
Vdd2
Power
supply (+5V)
40
PRGD
I
Serial
data
input for
receiving
instructions, coefficients,
and operators
transferred
from
the
microprocessor.
41
PRGCK
I
Serial
clock Input
for
PRGD.
Data
is
latched
by the
rising
edge
of this signal.
42 PFIGL
I
Latch
input
for internally latching serial
data
set
from
the
microprocessor. Active
when
set
"L".
43
DSP
I
Input select for
DSP
operations.
"H":
DSP
ON:
*L":
DSP
OFF.
44
MUTE
I
Mute
input.
Active
when
set "H".
I
Input
Capacity
Item
Symbol
Conditions Min.
Typ.
Max.
Unit
Input
pin*' ClH
3 5 PF
Input
pin*
2
Cin Input
mode 4
6 PF
'
1
All
pins
except
for
the
I/O.
*
2
I/O pin
161
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