Read From Dl Register - Sony CXD2701Q Data Book

SONY*
CXD1160AP-AQ
Delay
I/O
(delay
mode) and
register
(1)
32
bit
delay
mode
32
bit
Conditions
where
delay
mode
can be
realized
fS
£
--
fKCK
that
is
136
S,ai36
The
relation
between
data
to
write
in
DO
register
and
data
to
read from
Dl register
is.
•
DO
register
Cycle
to
cycle
66
:
data written
last in this
period
is
set
as
CH1
(n)
Cycle
67
:
write prohibit
Cycle 68
to
cycle (Ni-2)
:
data written
last in this
period
is
set
as
CH2
(rv)
I
Cycle (Ni-1), (Ni)
:
write
prohibit
•
Dl register
r
Previous cycle
134
to
cycle (Ni-2),
cycle
to
cycle
65
:
In
this
period
CH1
data
(n-r)
can read
1
Cycle 62
to
cycle
125
:
In
this
period
CH2
data
(n-r)
can
read.
I
Cycle
(Ni-1), (Ni)
:
read
prohibit
(2)
30
bit
delay
mode
30
bit
Conditions
where delay
mode
can be realized
fS
&
—
-
fKCK
that
is
123
N,il28
The
relation
between
data
to
write
in
DO
register
and data
to
read from
Dl register
is.
•
DO
register
Cycle
to
cycle
62
Cycle
63
Cycle 64
to cycle (Ni-2)
Cycle
(Ni-1), (Ni)
data
written last in this
period
is
set
as
CHI
(n)
write prohibit
data written last in this
period
is
set
as
CH2
(n)
write prohibit
• Dl register
[
Previous cycle
126
to
cycle
(Ni-2),
cycle
to
cycle 61
I :
In this
period
CH1
data
(n-r)
can
read
|
Cycle
62
to
cycle
125
:
In
this
period
CH2
data
(n-r)
can
read.
I
Cycte
(Ni-1), (Ni)
:
read prohibit
-
1
56
-