Sony CXD2701Q Data Book page 158

SONY*
CXD1160AP/AQ
(2)
Delay
I/O
output
register
Delay
I/O
output register
outputs twice during
1
sampling period.
For
one
of
those 2
instances the timing
is
the
same
as
for serial I/O.
For the other instance, the conditions
for
cycle n
where
transfer with
this
register
as destination
can
not
be executed
are
J_
fKCK
J_
fKCK
1
fKCK
8
B«
2
fs
~
4
i fB 2 fs
"
i
a
as
M=Q
[KCK]
j_ fttS
1
(
in
<
J_
fKCK
3
(
fKCK
2
fS
~
4
+
fB
n
2
fS
"
4
f
B
24
bit
clock
system
25 fKCK
1
.
.25
48
fS
"
4
48
IRQ
fS 4
32
bit
clock
system
33
fKCK
1
33
84 fS
"
4
<n
64
fKCK
fS
4
*ln certain cases,
as the
left
side
margin
is
not included, cycles
that
become
prohibited
are not included.
Please check
when
necessary.
Example
1)
tkck=6.144
MHz
fs=48
kHz
N-Ni = 128
(Cycle to cycle 127)
1 1
1
Delay
I/O input register
"i
<
-^-
128-4—-
=
60-—-
n
=;:6
Cycle
to
cycle
59
usable
Cycle 60
to
cycle 61
unusable
Cycle
62
to
cycle
123 .usable
Cycle
124
to
cycle
127 unusable
Delay
I/O
output register
24
clock
system
25
1
25 3
128-4
—
<n
<
128-2
48
4
4S
4
*!**'
<63
l2"
N=63
Cycle
to
cycle
62 usable
Cycle 63 unusable
Cycle 64
to
cycle
126 usable
Cycle 127
unusable
-
IS4-