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SONY
CX0270^Q
DRAM
Refresh
Normal
DRAM
refresh timings
are
as
follows:
256K
DRAMs:
4 msec/256
times
1M DRAMs:
8
msec/512
times
As
the
row address
of
the
DRAM
in
DSP
in
DSP
mode
is
incremented
each program
cycle
2/fs,
the
number
(N)
of
refresh
times during
2/fs
is
calculated
as
follows:
_2_
v
_J1_
< 4mS
8mS
fs
N
N
256
128
fs
512
fs=32kHz
fs=44.1kHz
fs=48kHz
NI4.0
N £2.9
NS2.7
In
order
that
all
low address
refresh
is
completed
within the
defined time
so
that
all
low
address
delay periods
are equal
to
N
time
accesses
(leading),
be
sure
to
set
relative
address
(rrs
to
ro).
Example:
When
N=4
times, set following
addresses:
<256K
D-RAM>
•
OOOOh
•
0040k
•
OOSOh
•
OOCOh
<1MD-RAM>
•
OOOOh
• 0080h
•
0100h
•
0180h
I
- 197-
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