Sony CXD2701Q Data Book page 177

SONY
CXD1355AG
Explanation
of
DSP
Block Diagram
FIR
1
1/2fs
down-sampling performed by
1
1th
FIR
filter.
FIR 2 Original
fs
up-sampled
signal
undergoes
DSP
signal
processing
to
1/2fs
by
1
1th
FIR
filter.
A/D Lch Register Register (ADL)
stores
L channel
16-bit
data
input
from FIR1
A/D Rch
Register Register
(ADR)
stores
R
channel
16-bit
data
input
from FIR1
D/A Lch Register Register
(DAL)
stores L
channel
16-bit
data output from FIR2.
Also used as
addition
1
st
register.
D/A Rch
Register Register
(DAR)
stores
R
channel
1
6-bit
data output from FIR2.
Also
used as a temporary
register
fordata output during
I/O
command
operations.
R1 Register
Register (R1) stores the received
16-bit
value during data I/O operations.
R2
Register
Register (R2) stores the
R1
register
data
16-bit
by
register transfer
command.
K-RAM
RAM
(K)
stores
2's
complement
format, 8-bit multiplication coefficients.
MOP
Register Register
(MOP)
stores the
16-bit
data
instruction
selected
from
the multiplication instruction
command,
ADL,
ADR.
R1
,
Ace
(1 6).
MPY
Executes each
operation
in
sequence:
MOP
(1 6)
x K
(8)
-* P
(20).
P
Register Register (P)
for
storing 16-bit x
8-bit
length results of multiplication 20-bit.
AOP
Selector Selects
DAL. R2, Ace
or
2ero from
the additional instructions.
Data
is
converted to 22-bit length format.
(AOP)
ADDER
Executes each
operation
in
sequence:
AOP
(22)
+
P
(20)
-* Ace
(22),
Ace
Register
Register
for
storing 22-bit
x
20-bit length results of
addition 22-bit
(Ace
(22),
Acc(16)).
Clipper
The
22-bit
length addition
result
in
Ace
(22)
is
used as
is
by
the
subsequent addition
command.
In
other operations,
when there are
16-bit length
operands and an
overflow
occurs, clipper
processing
is
performed
to
make
16-bit
length data
which
is
then output
to
Ace
(16).
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