Sony CXD2701Q Data Book page 156

SONY.
CXD11S0APWO
Example
1)
fKCK=6.44
MHz
fs=48
KHz N=N-=128
(Cycle
to
cycle 127)
Serial I/O input register
n=
iN,-4£n SN.-lS
•
(124
in S127
I
("Cycle
to
cycle 123
usable
"'
\
Cycle
124
to
cycle
127
unusable
1
3
I
Serial I/O
output
register
24
clock
system
\i-4
—
•
128<n
<
B-Z-
—128
4
48 4 48
B-lSn £1-1
n=K-l=K, -1=127
•{
Cycle 127
unusable
11
3
1
Serial I/O
output
register
32 clock
system N-4—
-
128<n
<
N-2
—
+
——
128
N-2-J-
<n
<K-
—
4 4
H-2£n
fiH-1
n=
1
B-ZSn SN-1
!
=
I
N,-2
sn
£1,-11 =
1126
Sn
S1Z7
)
.
f
Cycle
to
cycle
125 usable
1
Cycle 126
to
cycle
127 unusable
- 152