Sony CXD2701Q Data Book page 175

SONY
CXD1355AQ
Synchronization
i)
INIT re-synchronization
Re-synchronization
is
triggered
by
the rising
edge
timing of INIT.
After
the
synch
ronizati
on
circuit
clears out
the
previous synchronization timing,
synchronization
is
reset.
By
this
means
the differential
signal of the
rising
LRCK
signal
(LRCK
J") is
placed
in
the center
of
the synchronization
window (WINDOW).
ii)
LRCK
rising
signal position
The
synchronization circuit
is
controlled
by clock signal
CK1
(txiffi).
Depending on external IC conditions,
LRCK
is
triggered
by clock
SCK
(fxt),
During synchronization, the
rising
edge
of
LRCK
is
valid
between
the
two
points
shown
in
the
diagram below.
WCKO
1
SCK
TjmruinjmiirLJirL^^
tCKM
(WINDOW}
(
LRCKJ"]
BCK
LRCK
LRCK
rising
signal oositio^
I
Operation
at
POWER
ON/OFF
Output
timing clock
D/A
output
^
I71